Position Summary Meet the sales target by setting and managing global and regional sales status and strategy. Set operation strategies such as changing solution specifications and planning for upgrades, and manage for these strategies. Maintain competitiveness by setting and managing solutions and services pricing strategies. Maintain and promote the services by building operation strategies regarding performance management, statistics or big-data analysis, CS(Customer Service) and VOC(Voice of Customer) management, etc. Role and Responsibilities [Sales strategy setting] Drive the business growth strategy setting and portfolio, and oversee the global or regional sales status analysis and set sales strategy to meet the sales target. [Operation strategy] Drive to build the operational strategies such as changing solution specifications and planning for upgrades. [Price management] Review the solution's pricing policy and strategy. [Partner management] Drive the strategies for increasing Samsung solution sales by building relationships with partners to learn customer's needs and managing partners by region (via training, events, etc.). [Service operation] Drive the operation strategies such as performance management, statistics or big-data analysis and CS(Customer Service) and VOC(Voice of Customer) management to maintain and promote the services. Skills and Qualifications Has a wide range of experience, uses professional concepts and company objectives to resolve complex issues in creative and effective ways Works on complex issues where analyzing situations or data requires an in-depth evaluation of variables. Exercises judgement in selecting methods, techniques and evaluation criteria to obtain results. Determines methods and procedures on new assignments and coordinates other's tasks May manage a group such as coordinating activities regarding costs, methods and staffing Typically requires at least 8 years of related experience and a Bachelor's degree; or 6 years and a Master's degree; or a PhD with 3 years

Roles and Responsibilities Independent Verification Ownership of IP DV. Collaborating with various across functional team at multiple geo location as part of execution. Expected to work hands on to close all aspects of verification activities including Testplan creation, building testbenches based on standard DV methodology, developing DV Infrastructure (Coverage/Regression/Simulation Scripts) Must have experience in developing test benches for IP/Subsystems/SoC. In depth knowledge and hands on experience in the execution of verification of SoC/SS/IP DV Previous experience of independently driving IP DV projects from Ability to lead a team by providing technical guidance as well as by part of execution by debugging and SoC architecture understanding capabilities Strong hands on experience with common verification tools and methodology including UVM/System Verilog/CDV/MDV, DV signoffs Must have a strong domain expertise in one or more following areas - CPU/Cache Coherency/CPU Pipeline/Cache/Branch Prediction/MMU Experience in Hybrid testbenches (SV, C/C++, Python) and C/C++ based CPU vectors/stimulus based verification is desirable Experience/Exposure to RISC-V Core DV or any other Core DV is highly preferred Experience - 7-10 Years Qualifications B.Tech/B.E/M.Tech/M.E

Role and Responsibilities About Samsung Semiconductor India Research (SSIR) Samsung Memory as a global industry leader for more than two decades, pioneered in milestone technologies like DRAM, NAND Flash and widest product portfolio based on these technologies. Memory software team, SSIR Bangalore plays a key role in maintaining this leadership by continuous innovation and applying it to a real life products. We provide the opportunities for you to share and build up your knowledge and expertise, and collaborate to drive innovation forward. At Samsung, you will witness your ideas come to life in new products and solutions that shape the future. Here is an opportunity to be part of this talented team where you can also be an innovator and make bigger impact As a Firmware Engineer at Samsung Semiconductor India Bangalore, you will be involved in Design, Implementation and Integration of various firmware subsystems of Flash storage products (SSDs, Mobile Storage using NVMe/UFS/SAS/SATA interfaces). You will be associated with Product's development life cycle ranging from Product inception to Qualification or any specific area defined by specific assignment. You will also be responsible for providing technical inputs or guidance to improve and adhere to software development and quality assurance processes necessary to ensure the firmware consistently meets the required functionality, re-usability, reliability and performance to ensure Samsung SSDs meet their design targets. The main areas of responsibility for this person/position are: SSD/Flash storage Products: Develop firmware subsystems that meet or exceed the requirements of technical Spec matrix including but not limited to Performance, Reliability, Endurance and Functionality Firmware Quality Assurance: Develop a firmware functional unit or integration test capability that ensures all the firmware subsystems meets the quality and functional KPIs Multi-functional Teamwork: Develop and maintain collaborative, open and constructive relationships with peers and management Personal Development: Work to continuously improve your technical skills/capability and communication/presentation skills Team Development: Provide technical capability that continuously improves team involvement, morale and productivity Required (Mandatory) Individual Contributor: Strong Programming skills in C/C++, Data structures/Algorithms Sound knowledge on NAND flash firmware stack like front end/back end etc. (FTL, Host Interface, Flash Interface etc.) Previous work experience on any of the storage protocols (eMMC/UFS/SCSI/SATA/NVMe) Knowledge on scripting languages like Perl/Python/Shell etc. and Batch/Make/CMM scripting etc. Strong debugging skills in Visual Studio, on ARM based SOC using Lauterbach T32, Logic Analyzers etc. Issue re-production/fixing, Logging/Diagnostics etc. Experience in Requirement analysis, Architecture, Design, Development and UT/IT Trouble shooting complex issues such as scalability & performance issues, memory leaks, memory corruption and Code size issues & optimization techniques Excellent skills on written/verbal communications and complex design articulation/presentation Demonstrated team player or technical leader in a dynamic, fast moving and fast growing product development environment Experience 6 to 15 yrs Qualifications B.Tech/B.E/M.Tech/M.E

Roles and Responsibilities Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis, Place and Route, STA, timing and physical signoffs Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC clean up, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through recent successful SOC tape-outs Experience 5+ Years of experience Qualifications B.Tech/B.E/M.Tech/M.E

Position Summary Senior Analog Designer with relevant experience of 512 years in Analog and Mixed-Signal Design. Must have full IP design experience in at least one of the domains listed below. Roles and Responsibilities Low-jitter and high-frequency PLL design experience, including both LC and ring-based PLLs General-purpose ADC and thermal sensor IP design experience High-speed SerDes design experience LDO, BGR, and other power management block design Ideal candidate should be ready for challenging design assignments and exposure to silicon validation Opportunity to gain full exposure to the IP design cycle in advanced Samsung Foundry processes (4nm and below) Skills and Qualifications B.Tech / M.Tech / Ph.D. in relevant fields

Role and Responsibilities SRAM design group in Bangalore develops various types of SRAMs, Registerfiles and ROMs in advanced technology nodes like 4nm, 2nm and beyond. The team is responsible for delivering highly competitive memories for the SAMSUNG Foundry customers. Provides a unique opportunity to the individuals who are willing to innovate and solve the most challenging problems in the field of circuit design. Samsung Foundry being a pioneer in new device technology, it creates ample opportunities for the circuit designer to innovate and design highly competitive IPs. Design highly competitive circuits to meet performance/power specifications requested by customers. Guide and lead a group of engineers to deliver the SRAM IP in the given timelines. Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design. Own the responsibility from SPEC to GDS and DK delivery. Review circuits, robustness reports and identify potential robustness issues. Review layouts and suggest improvement areas to achieve competitive PPA. Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC. Must be able to communicate effectively across different teams. Skills and Qualifications Master/Bachelor in electronics Working experience (10+ years) preferably in Memory design Understanding of RC network and FinFET fundamentals are necessary Custom or Compiler SRAM/ROM development experience Fundamentals of process variability and its effect on memory design Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM) Strong understanding of circuit design fundamentals Critical path modeling concept, various types of models (RC, C, Pi, ladder) Good knowledge of semiconductor physics, like knowledge of FinFET function, parasitics etc Analysing layout and understanding of LLE effects Bachelor's / Master degree in Computer Science, Electrical/Electronics Engineering, Engineering and 10+ years of experience in circuit design

Roles and Responsibilities Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies Executed scan & MBIST insertion, ATPG and verification at full chip level Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts Generate, review and validate DFT constraints to achieve timing closure of high speed design Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations) Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved Understanding of Power Estimation/Management for DFT modes is preferred Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples Strong written and oral communication skills Experience 5+ Years Qualifications B.Tech/B.E/M.Tech/M.E

Position Summary Complex SOC Top Physical Implementation for next generation SoCs by means of Synthesis, Place and Route, STA, timing and physical signoffs Role and Responsibilities Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Skills and Qualifications Experience in top level floorplanning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through 4+ recent successful SoC tape-outs Should have 8 14 years of experience in physical implementation and design

Role and Responsibilities About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segments in component solutions, featuring industry-leading technologies in System LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions, AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPs and much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. Roles and Responsibilities 5+ years of experience in full chip DFT architecture, implementation, timing closure and post silicon validation. Expertise required in the following areas: Scan architecture planning, pin mixing and scan compression planning, optimization for pattern volume for SA and TD pattern sets, scan synthesis, power optimization techniques in test modes MBIST architecture planning, repair architectures, insertion, verification Analog and mixed signal IP testing architecture and verification including IPs such as PLLs, PHYs Timing closure of scan, MBIST and other test modes, writing SDCs, understanding of timing exceptions wherever required, debugging timing issues with PD team Timing GLS, debug of fails in simulations Post silicon validation, interpretation of tester results, debugging IR drop issues, diagnostics of silicon failures Understanding of JTAG operation and debug required. Understanding of iJTAG protocol desirable Understanding of functional test cases, IO testing, testing of ARM processor cores Ability to lead a team across all aspects of DFT, interact with RTL, physical design teams for DFT implementation, anticipate risks, plan project timelines and milestones Experience 5+ Years Qualifications B.Tech/B.E/M.Tech/M.E Disclaimer Samsung Semiconductor India Research (SSIR), a division of Samsung R&D India - Bangalore Pvt. Ltd is dedicated to employing a diverse workforce and providing Equal Employment Opportunity to all individuals, regardless of their religion, gender, age, marital status, gender identity, status as a protected veteran, genetic information, status as a qualified individual with a disability, or any other characteristic protected by law.

This position is within Samsung India Electronics Limited with D2C Online VD sales Division, headquartered in Gurgaon, India. 2-4 years of experience in Growth / Performance Marketing, preferably in a ecommerce setup. Passion for online shopping behavior, digital trends, and consumer psychology. Strong knowledge and hands-on experience in Digital Marketing & Product Management/GTM. This candidate executes Media campaigns, & works on enhancing customer journey (UI/UX) and ensures share of voice & brand equity/visibility in the digital medium landscape. Role and Responsibilities Plan, execute, and optimize paid marketing campaigns across Meta, Google, YouTube, and other digital platforms. Manage and improve performance marketing KPIs ROAS, CAC, CTR, CVR, etc. Build and execute CRM and retention journeys using MoEngage (Email, Push, SMS, In-App). Segment users and personalize communication to boost engagement and repeat purchases. Optimize landing pages and product pages to improve conversion rate and AOV. Collaborate with design/content teams for ad creatives, banners, and emailers. Run A/B tests across channels and website elements to drive incremental growth. Analyze campaign and funnel performance using tools like GA4, MoEngage, and internal dashboards. Present actionable insights and weekly/monthly performance reports to leadership. Stay updated with industry trends, platform updates, and new tools to keep strategies fresh. Skills and Qualifications Full time MBA Tier 1 College preferred. 2-4 years of experience in Growth/performance marketing/Product management/ role. Intelligent- passionate & motivated with high energy levels ability to work in a fast paced environment Values team and input and collaboration in working towards a company goal/target Resilience: this is a challenging role. It requires tenacity, positivity and a clear head under pressure there will be many different projects underway and you need to keep your head in sometimes fast paced meetings Collaborative: the ability to build a network, understand different points of view, overcome objections, deliver a vision, a plan and then make it happen by working with and through others

Role and Responsibilities Good understanding and experience in writing C/C++/Python based test script is must. Experience in Compliance & Test Dev, Test Design, Product Engineering, Debug and Troubleshooting, E2E automation & mechanization, AI/ML in QA (Analytics). Experience in understanding and writing test cases and scripts as per Protocol specification. SSD (SAS/SATA/NVMe) specification preferred. Good knowledge in Stress and performance test suite development. Exposure to debugging tools like TRACE32/Lecory Protocol Analyzer/DSO/LA is preferable. Possess good understanding of Protocols and Firmware - SSD (SATA/SAS/NVMe) Protocol/firmware (FTL) preferred. Ability to troubleshoot and analyse failure reported during test cycle or failures reported from field. Attitude towards test planning, test development and test execution. Excellent verbal/written communication and interpersonal skills with ability to multi-task. Self-motivated with good team player role demonstrated in past.