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Memory Team - Physical Design Engineer

Memory Team - Physical Design Engineer

Samsung

8 - 14 years

8 - 14 Lacs

Bengaluru / Bangalore Karnataka India

Posted:1 month ago| Platform: Foundit logo

Apply

Skills Required

Physical Design Timing Closure Synthesis floorplanning

Work Mode

On-site

Job Type

Full Time

Job Description

Position Summary Complex SOC Top Physical Implementation for next generation SoCs by means of Synthesis, Place and Route, STA, timing and physical signoffs Role and Responsibilities Hands on experience doing physical design and timing closure of complex blocks and full-chip designs Should have strong understanding of timing, power and area trade-offs and optimization of PPA Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ Expertise in block level and full-chip SDC cleanup, Synthesis optimization, Low Power checking and logic equivalence checking Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling) Familiar with typical SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence Skills and Qualifications Experience in top level floorplanning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level Should have gone through 4+ recent successful SoC tape-outs Should have 8 14 years of experience in physical implementation and design

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Memory Team - Physical Design Engineer