Senior Design Verification Engineer

Job Description

Roles and Responsibilities Independent Verification Ownership of IP DV. Collaborating with various across functional team at multiple geo location as part of execution. Expected to work hands on to close all aspects of verification activities including Testplan creation, building testbenches based on standard DV methodology, developing DV Infrastructure (Coverage/Regression/Simulation Scripts) Must have experience in developing test benches for IP/Subsystems/SoC. In depth knowledge and hands on experience in the execution of verification of SoC/SS/IP DV Previous experience of independently driving IP DV projects from Ability to lead a team by providing technical guidance as well as by part of execution by debugging and SoC architecture understanding capabilities Strong hands on experience with common verification tools and methodology including UVM/System Verilog/CDV/MDV, DV signoffs Must have a strong domain expertise in one or more following areas - CPU/Cache Coherency/CPU Pipeline/Cache/Branch Prediction/MMU Experience in Hybrid testbenches (SV, C/C++, Python) and C/C++ based CPU vectors/stimulus based verification is desirable Experience/Exposure to RISC-V Core DV or any other Core DV is highly preferred Experience - 7-10 Years Qualifications B.Tech/B.E/M.Tech/M.E