979 Floor Planning Jobs - Page 19

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Client Welcome & Assistance Greet walk-in clients, visitors, and potential buyers warmly. Ensure a pleasant and professional first impression of the company. Client Coordination Schedule site visits, follow up on appointments, and coordinate with the sales team. Escort clients during site visits or coordinate with the designated representative. Customer Experience Management Understand client needs and guide them to appropriate project offerings. Provide brochures, floor plans, and explain amenities when needed. CRM & Data Handling Maintain visitor records and update client information in the CRM system. Share feedback and insights from client interactions with the sales and marketing teams....

Job Description Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes. Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering (VLSI Design) Hands-on design knowledge on both Digital custom, Analog & mixed signal design environment. 4+ years ...

Job Description Will be technically driving team Custom Circuit IO and Datapath solutions for next generation Memory in advanced CMOS technology nodes. Will work on architecture of High speed IO and DataPath solutions to meet the specifications and product requirements Work closely with team and actively participate in technical discussions and reviews. Pro-actively get design issues/problems solved. Contribute to or propose innovative design solutions and design methodologies. Qualifications Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering Hand-on design knowledge on both analog & mixed signal design environment. 8+ years of Experience on IO circuit blo

Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, sc...

TCS is hiring for JDA Planogram Developer role !! Qualification:- Minimum 15 years of regular, full-time education (10 + 2 + 3) is mandatory. Shift - 4:00 PM 2:00 AM Job Description- The Category Alignment Space Management Analyst is the liaison between merchant, cross-functional partners and field organization. Responsible for analyzing data to create planograms using our JDA/Blue Yonder software and BDM/Walgreens space management systems, while also possessing the ability to interpret and present the 'why' behind decisions. Responsible for capturing the vision and visual merchandising strategy of our merchant partners Responsible for timely delivery of clear, concise playbooks to the plano...

ofAbout the Job 3 to 8 years of relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and pref...

In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. - Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification Should have experience on programming in Tcl/Tk/Perl

You are a Senior Principal Analog Layout Engineer at OnSemi, responsible for developing high-quality layout for complex AMS IP blocks including voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, and drivers. You will lead a team of 4-6 engineers, review their work, and drive continuous quality improvements. Your responsibilities include estimating schedules, managing manpower resources, and planning layout activities to ensure timely completion. In this role, you will contribute to area estimation, optimization, floor planning, power routing, shielding, and physical verification such as DRC, ERC, LVS, and ESD. Additionally, you will support the team in taping o...

Following our Business Code of Conduct and always acting with integrity and due diligence Identifying operational improvements and finding solutions by applying CI tools and techniques Responsible for completing tasks and transactions within agreed KPIs Knows and applies fundamental work theories/concepts/processes in own areas of work Planning micro(product) or macro(category) layouts and adjacencies for stores in line with agreed principles and strategies Using Space and Floor Planning tools to create and maintain high quality plans for stores Keeping self up to date with process changes Following the defined Quality Assurance Processes and framework

Experience : 4-10 Yrs Location : Blre 4-10 years experience with Bachelors degree in Electronics Engineering or equivalent Knowledgeable in all aspects of deep submicron ASIC design flow. Knowledgeable in Static Timing Analysis, Power Analysis and Innovus. Hands-on experience in developing and modifying PD-flow/EDA-tools scripts/recipes using TCL/SHELL/PYTHON programming languages. Experience in developing PD metrics dashboard scripts for QOR tracking is a plus Experience in modifying STA constraints to check timing closure feasibility Experience in various clock implementation strategies (Multi-point CTS, Flex-H, Custom-CTS) for meeting block level and full chip level latency and skew targe...

At Synopsys, you are at the heart of the innovations that are changing the way we work and play, from self-driving cars to Artificial Intelligence, the cloud, 5G, and the Internet of Things. As a part of our Analog Mixed Signal IP Team, we are looking for an Analog Mixed Signal (A&MS) Layout Engineer to join our talented team. If you are an experienced A&MS Layout Engineer seeking to work with experts in high-end Analog Mixed Signal design using the latest process technologies and be a valuable team player, then this position might be perfect for you. You will have the opportunity to work with the world's number one IP provider, collaborate with experts from around the globe, and join a high...

Wipro Limited is a leading technology services and consulting company dedicated to creating innovative solutions that cater to the most complex digital transformation requirements of clients. With a global presence spanning 65 countries and a workforce of over 230,000 employees and business partners, Wipro is committed to helping customers, colleagues, and communities thrive in an ever-evolving world. For more information, please visit www.wipro.com. As a Physical Design Lead, you will be based in Bangalore, Hyderabad, or Pune with a minimum of 8 years of experience. Your responsibilities will include handling Netlist2GDSII Implementation tasks such as Floor planning, Placement, CTS, Routing...

Embark on a transformative journey as a ?Device Engineering? at Barclays, where you'll spearhead the evolution of our digital landscape, driving innovation and excellence You'll harness cutting-edge technology to revolutionize our digital offerings, ensuring unparalleled customer experiences At Barclays, we don't just anticipate the future we're creating it, To be successful in this role, you should have below skills: Expert-level PowerShell scripting (e-g , modules, API integrations), Deep knowledge of Windows imaging (capture/customize WIM files, DISM, WinPE), Experience with device drivers, BIOS/UEFI, and hardware compatibility, Proficiency in patch management and OS servicing strategies,...

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

We are looking for a Digital/Memory Mask Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs.NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, an...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work , to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do thei...

We are looking for a Digital/Memory Mask Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs.NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, an...

We are looking for a Senior Digital/Memory Mask Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can add...

Wipro Limited (NYSEWIT, BSE507685, NSEWIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role _x000D_ Role Purpose The purpose of this...

Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, sc...

Responsibilities - Work with the business and IT team to identify, analyze, and translate business requirements into comprehensive design documents (RDD, FDD, TDD etc.,) - Thorough understanding of Floorplan & Factoring flow and Financial products in the Wholesale Financing products. - Hands on experience on .NET X, HTML, .Net Core, WEB AP. - Lead and be part of strategy in ERP system implementations, upgrades, and support with strong focus on ensuring that Finance, Treasury and Accounting Data is following policies as well as securitization servicing and reporting requirements - Thorough understanding in requirement analysis and technical evaluation, with a strong command of cloud technolog...

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in ...

Job Description: Strong understanding of Physical Design with hands-on experience in RTL2GDS flow. Ability to close tiles/blocks including timing, noise, power, IR, phyV, conformal equivalence, and signoff checks. Exposure to advanced technology nodes (7nm and below) and related design challenges. Experience with the Synopsys tool suite is required. Knowledge of high-frequency design (>2GHz)