Digital Front-End Lead

Tekskills

8 - 13 years

20 - 35 Lacs

hyderabad chennai bengaluru

Posted:3 hours ago| Platform:

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Skills Required

rtl coding verification planning soc design asic synthesis rtl rtl design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Role & responsibilities

Digital Front-End Lead

Verification Leader with design exposure

* Target products are not FPGA-based.*

*

Key Skills - Priority Level (1-5)

Chip Level Verification 5
Chip-Level Use Case Understanding
Verification Plan Formulation, Management, and Review
Extraction of verification items and formulation of verification program stimulus specifications
Building Dynamic & Static Verification Environments
Gate-Level Simulation with Back-Annotated Delays
Management -5
Leadership Experience, Project Planning, Collaboration with Backend and Analog Team
DFE Team Management
Documentation
Continuous Improvement Suggestions
Functional Safety Standards
RTL Design & Quality Verification - 4
RTL Quality Control
RTL Coding Skills (Verilog HDL/System Verilog)
RTL Quality Check Execution; EDA Tools for RTL Quality Checks
Architecture Design – 3
Chip-Level System Architecture Design
Block-level microarchitecture design
Constraint Creation and Synthesis (SDC/STA) - 3
Timing and synthesis constraints
Synthesis trial and STA report confirmation
Chip Level Assembly – 3
Chip-Level Assembly Using EDA Tools
Power System Design- 3
Multi-Power Domain Design
Power System Model Design
Testing, On-Board Evaluation, and Mass Production Support- 3
Evaluation Flow (Actual Machine Bring-up, ATE Pattern Generation)
Evaluation Specifications (test items such as SCAN, BIST, and cutout tests)
Power Estimate- 2
Power Analysis Using EDA Tools and Design Feedback
Power Estimation During Feasibility Stage

Preferred candidate profile

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