Posted:1 day ago|
Platform:
On-site
Part Time
LNT/DE/1553239
Knowledge & Posting Location
DFT
VLSI DESIGN FOR TESTABILITY - DFT
SCAN INSERTION
ATPG - VLSI AUTOMATIC TEST PATTERN GENERATION
Minimum Qualification
BACHELOR OF ELECTRICAL ENGINEERING (BEE)
Purpose of the Role:
The Design for Testability (DFT) engineering organization at L&T Semiconductor Technologies (LTSCT) pioneers innovative methods and technologies in the areas of DFT architecture, verification, and post-silicon bring-up of state-of-the-art semiconductor chips, such as System on a Chip (SoCs), developed using the latest semiconductor technology nodes.
Areas of Responsibilities:
Implement various DFT techniques, including:
Conduct DFT simulations and analyze results to ensure comprehensive test coverage and high quality.
Debug and resolve DFT-related issues throughout the design process.
Larsen & Toubro
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