Design Verification Manager

12 - 18 years

60.0 - 90.0 Lacs P.A.

Bengaluru

Posted:3 weeks ago| Platform: Naukri logo

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Skills Required

System VerilogcoverageCadenceMentorPerlMS ProjectJIRAUVMregressiontest caseTCLSynopsysPython

Work Mode

Work from Office

Job Type

Full Time

Job Description

Exp: 12 to 16 years B.E./B.Tech or M.E./M.Tech in Electronics semiconductor/VLSI services with at least 3–5 years in delivery or practice leadership roles. Experience in System Verilog, UVM, test case, coverage, regression.

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