Design Verification Engineer

Hi, Greetings from EWarriors Tech Solutions. We are hiring for the below position: Role: Sr/Lead Design Verification Engineer Location: Siruseri, Chennai (Onsite – 5 Days) Experience: 6+ Years Notice: Immediate to 15 days Key Responsibilities: Perform functional verification at block and chip level for complex ASIC/SoC designs. Build UVM-based testbenches from scratch for new IPs or subsystems. Develop and execute detailed verification test plans based on design specifications. Write directed and constrained-random test cases; debug simulation failures. Perform coverage analysis (functional and code) and drive closure. Work with RAL (Register Abstraction Layer) to verify register-level functionality. Develop and validate assertions (SVA) for protocol and functional correctness. Collaborate closely with RTL, DFT, and GLS teams to ensure alignment across design phases. Participate in multiple tape outs , ensuring verification quality and delivery. Required Skills: Strong hands-on experience with System Verilog and UVM methodology . Solid knowledge of SoC/ASIC architecture and verification lifecycle. Hands-on experience in writing testbenches, stimulus, checkers, monitors, and scoreboards . Strong debugging skills using simulation tools like VCS , Questa . Experience with functional and code coverage . Familiarity with Register Abstraction Layer (RAL) modeling and verification. Excellent analytical and problem-solving skills. Strong communication and teamwork abilities. Candidate Requirements: Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields. Experience: 6–10 years of relevant experience in ASIC/SoC design verification. Must have contributed to at least two one or more successful tapeouts . If interested, kindly share the resumes to *bharathi@ewarriorstechsolutions.com* or contact @8015568995. Job Type: Full-time Pay: ₹1,200,000.00 - ₹1,500,000.00 per year Schedule: Day shift Morning shift Experience: SOC: 4 years (Preferred) ASIC: 4 years (Preferred) Register Abstraction Layer (RAL): 3 years (Preferred) Total work: 6 years (Preferred) System Verilog: 5 years (Preferred) UVM: 5 years (Preferred) VCS/Questa: 4 years (Preferred) Work Location: In person