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Design Verification Engineer

Design Verification Engineer

Luxoft

3 - 7 years

12 - 16 Lacs

Hyderabad

Posted:2 hours ago| Platform:

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Skills Required

python digital design perl system verilog unix internals asic soc verification simulation design verification document verification uvm vhdl verilog rtl design axi fpga fpga design embedded systems linux debugging bash code review pcie unix

Work Mode

Work from Office

Job Type

Full Time

Job Description

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems.At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities

Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage.

Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies.

Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs.

Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements.

Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency.

Work in Unix/Linux environments for development, simulation, and regression testing activities.

Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones.

Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices.
Skills Must have

1 position6+y, 1 position4+y

Strong in digital design.

Skills in ASIC / FPGA verification (directed test or System Verilog / UVM)

A good knowledge of simulation flow

Good basis in scripting Python, Perl, Bash..

Proficiency in Unix environment.

Good communication skills
Nice to have

Bachelor's/Master's in ECE

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Design Verification Engineer