Design verification engineer

Gigaops Global Solutions

5 - 15 years

7 - 11 Lacs

bengaluru

Posted:8 hours ago| Platform:

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Skills Required

design verification telecom asic automation semiconductor fpga soc perl uvm python

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Job Type

Full Time

Job Description

Role & Responsibilities

Develop and execute formal verification plans for digital blocks and SoC integrations using SystemVerilog and UVM methodologies.
Implement directed and constrained random testbenches, stimulus generators, and assertions to validate RTL against specifications.
Run simulations on industry simulators (VCS, Questa/Xcelium), analyze failures, debug RTL/testbench issues, and drive fixes with design teams.
Measure and improve functional coverage; define coverage goals and close coverage holes using coverage-driven strategies.
Automate regression flows and build verification infrastructure using scripting (Python/Tcl/Perl) and CI tools to speed up turnaround.
Collaborate with architecture, synthesis, timing, and validation teams to support silicon bring-up, gate-level verification, and signoff activities.

Skills & Qualifications

Must-Have

Proven experience with SystemVerilog for design verification
Practical knowledge of UVM testbench methodology
Experience with industry simulators (Synopsys VCS, Mentor Questa)
Strong RTL verification skills (coverage-driven, constraint-random)
Assertion-based verification (SVA) experience
Scripting for automation and debug (Python, Tcl, or Perl)

Preferred

Experience with formal verification tools (e.g., JasperGold)
Exposure to FPGA prototyping and emulation platforms (Palladium, Veloce)
Low-power verification knowledge (UPF) and gate-level signoff experience

Benefits & Culture Highlights

Hands-on, fast-paced engineering environment with clear ownership and growth paths.
Opportunities to work on full verification lifecycle from IP to SoC and silicon bring-up.
Collaborative on-site team culture emphasizing technical excellence, mentorship, and measurable impact.

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