Sr. Design Verification Engineer

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SENIORSILICON DESIGN ENGINEER

THE ROLE:

We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:

We are looking for a dynamic candidate who will have great opportunity to work on the state-of-the-art products with leading verification methodology. Take your current verification expertise and apply that to state-of-the-art products involving complex protocols like PCIE, CXL and AXI.

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Develop/Maintain tests for functional verification and performance verification at the core level
• Architect self-checking constraint random test benches using UVM methodology for IP level verification.
• Build various test bench components and scoreboard.

• Create block level verification plan, test plans and full chip test plans.

• Execute on the test plans, review the test plan with design and architecture and incorporate the feedback

• Work with designers to get the coverage closure

• Port the block level tests to full chip test bench

• Integrate VIPs as needed

• Provide support t software, validation and emulation teams as needed.

• Work on other aspects of verification like CDC, power aware verification (UPF) and gate simulation.

PREFERRED EXPERIENCE:

• Prior experience in architecting and developing self-checking constrained random verification environment using System Verilog and UVM verification methodology.
• Execution of test plan, debugging failures, write functional coverage objects and review the code coverage and function coverage with design team
• Good understanding of object-oriented programming concepts.
• Prior experience with PCIE or CXL Protocol.
• Prior experience in verifying is system/sub system level involving multiple blocks.
• Prior experience with protocols such as AXI, APB, AHB etc.
• Programming in scripting languages like Python, TCL and Perl.
• Excellent communication skills
• Good problem-solving skills and analytical ability
• Familiarity with EDA tools for simulation, debugging, coverage analysis, CDC, LINT etc.

ACADEMIC CREDENTIALS:

• Bachelors degree in computer engineering/Electrical Engineering

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