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Design For Testability Engineer, Silicon

Design For Testability Engineer, Silicon

Google

5 - 10 years

22 - 27 Lacs

Bengaluru

Posted:1 day ago| Platform:

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Skills Required

Design verification STA Data analysis JTAG DFT static timing analysis atpg Perl Silicon

Work Mode

Work from Office

Job Type

Full Time

Job Description

Minimum qualifications:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test including silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing.
Experience with ATPG, Low Value (LV), Built-in self test
(BIST) or Joint Test Action Group (JTAG) tool and flow.

Preferred qualifications:

Experience with a programming language like Perl with Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC) and DFT timing and Static Timing Analysis (STA).
Knowledge of performance design DFT techniques.
Knowledge of the end to end flows in Design, Verification, DFT and Partner Domains (PD).
Ability to scale DFT.

About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

Work on a team of Design for testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, Static Timing Analysis (STA) checks.
Write a Pattern delivery using Automatic Test Pattern Generation (ATPG).
Work with Silicon bring-up.
Work on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug and deliver debug patterns. Perform Silicon data analysis.

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Design For Testability Engineer, Silicon