Job
Description
Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 5 years of experience in characterizing standard-cells or memory. 5 years of experience in static timing analysis and simulation. Preferred qualifications: Master's degree in VLSI Integration, Computer Engineering, Electronics Engineering, or a related field. Experience in spice and statistical circuit simulators, including FineSim, HSpice, Spectre, and Solido. Experience in Practical Extraction and Report Language (PERL)/Shell/Transaction Control Language (TCL) scripting or similar languages. Understanding of Complementary Metal-Oxide-Semiconductor (CMOS) circuits and timing concepts (e.g., setup, hold). Ability to automate repeatable tasks to improve efficiency/productivity using the scripting languages. Proficiency with industry-standard Electronic Design Automation (EDA) tools for implementation and signoff. About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google Silicon team develops custom silicon solutions that provide differentiated user experiences in Google hardware products and optimize performance and power for the use cases. This includes SoCs and other mixed signal, logic, and sensor integrated circuits for our product portfolio. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Work with Post-Si teams to improve and debug Vmin and yield related issues. Explore and specify new custom circuit opportunities for optimized Power Performance Area (PPA) for high-performance, low-power subsystems. Work with the testchip teams on latest process nodes to build, validate and characterize custom IPs. Build automation for circuit design simulation and analysis. Work with cross-functional teams on circuit design, physical design and sign-off methodology teams. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form . Show more Show less
