Posted:2 weeks ago| Platform: Foundit logo

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Job Type

Full Time

Job Description

  • 8+ years of experience in

    Layout automation,

    Physical Verification, or related domains.
  • Experience in customizing a design environment, automation methodologies and utilities to increase memory layout productivity.
  • Working experience in Place and Router flows for custom memory layouts with industry standard tools like

    Cadence Virtuoso,

    Synopsys Custom Compiler, Pulsic Unity, Itools etc.
  • Working experience in

    PDN

    analysis tools like

    Totem/VoltusXFA/XA

    is preferable.
  • Working experience of Physical Verification flow and analyzing/debugging

    DRC, ERC, LVS,

    DFM, Antenna Calibre/ICV rule deck issues is plus.
  • Good understanding of advanced

    CMOS

    process manufacturing and layout design rules,

    EMIR, RC-Extraction, ESD,

    and Latch-up.
  • Good understanding of programming fundamentals, as well as exposure to various programming languages including Skill (Cadence), Perl, Python, Tcl.
  • Working knowledge of Linux is a must.
  • Excellent problem-solving skills with attention to detail.
  • Ability to work in a dynamic environment.
  • Proficiency in working effectively with global teams and stakeholders.

Education:

  • A bachelor's or a master's degree in Electronics, Electrical or Computer Engineering.

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