As a candidate for the role at Ceremorphic AI, you will be responsible for owning and driving the physical implementation of next-generation SOCs. Your role includes the following key responsibilities: - Understand the requirements and define physical implementation methodologies. - Collaborate with architecture, design, front end, and CAD teams to deliver high-quality physical designs. - Implement and verify designs at all levels of hierarchy in the SOC. - Interact with foundry over matters of technology, schedule, and signoff. - Supervise resource allocation and scheduling. In order to excel in this position, you should possess the following key requirements: - Hands-on expertise in Floorplanning, Power planning, Logic and clock tree synthesis, Placement, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR. - Full chip/ top-level expertise in multiple chip tape-outs. - Good understanding of SCAN, BIST, and ATPG. - Strong background in TCL/Perl programming is a must. - Expertise in double patterning process nodes is desirable. - Expertise in Cadence RTL-to-GDSII flow is preferred.,

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ASIC Physical Design Engineer