ASIC Physical Design Engineer Ceremorphic

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

The role at Ceremorphic AI hardware involves owning and driving the physical implementation of next-generation SOCs. The responsibilities include understanding requirements, defining physical implementation methodologies, collaborating with various teams, implementing and verifying designs, interacting with foundry, and supervising resource allocation and scheduling. The ideal candidate should have hands-on expertise in floorplanning, power planning, logic and clock tree synthesis, placement, timing closure, routing, extraction, physical verification (DRC & LVS), crosstalk analysis, and EM/IR. Additionally, full chip/top-level expertise in multiple chip tape-outs, understanding of SCAN, BIST, and ATPG, strong background in TCL/Perl programming, and expertise in double patterning process nodes are required. Preferably, expertise in Cadence RTL-to-GDSII flow is also desired.,

Posted 2 days ago

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.