Asic Design Engineer

5 - 8 years

10 - 20 Lacs

Posted:2 days ago| Platform: Naukri logo

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Work Mode

Work from Office

Job Type

Full Time

Job Description

Hi all here we have openings for ASIC design engineer. Pls find below jd

ASIC Design Engineer

Location : Hyderabad.

Mode : work from Office

Notice period: 0-30days

  • Understanding of IP design, RTL coding, Verilog/SV
  • Proficient in RTL simulation tools
  • Knowledge of High-speed interfaces PCIe, Ethernet, DDR AMBA AXI/AHB/APB Protocol
  • Strong knowledge of IP/SOC design methodologies
  • Experience with scripting languages including Perl, Python, Unix shells and Make files.
  • Excellent communication skills and experience working with global teams Setup ASIC QA flows for RTL design quality checks.
  • Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains
  • Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps.
  • Clock constraints, false paths, multi-cycle paths, IO delays, exceptions, and waivers.
  • Checking the flow errors, design errors & violations and reviewing the reports.
  • Debugging CDC, RDC issues and propose the RTL fixes.

Interested candidates pls send there resume to below mail id

Nagapriya.p@tekpages.in

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