5 years
0 Lacs
Posted:1 day ago|
Platform:
On-site
Full Time
Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. The solutions embed high-performance AI into edge devices to create a smarter, safer, and more enjoyable world. Edge AI is on the brink of a boom, and looking forward to playing a significant role in it.
Experience 5-20Years
This is what you are responsible for
Develop verification environments for modules, subsystems, top level and FPGA
Build models, checkers and random test frameworks using SystemVerilog and UVM
Participate in Low power analysis (UPF), power estimation, C modeling
Perform lint, CDC, code coverage, functional coverage
Formal verification of modules using SVA assertions
Necessary Qualifications
Experience in verifying complex subsystems and ASICs
Experience with building scalable verification environments from scratch
Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc.
Exposure to FPGA emulation platforms, silicon bringup, and board debug
BTech/MTech in EE/CS with any level of experience
Please do reach me on +91-9071106778
Connectpro Management Consultants Private Limited
Upload Resume
Drag or click to upload
Your data is secure with us, protected by advanced encryption.
Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.
We have sent an OTP to your contact. Please enter it below to verify.
Instantly access job listings, apply easily, and track applications.
Hyderabad, Telangana, India
Salary: Not disclosed
Salary: Not disclosed
Hyderabad, Telangana, India
Salary: Not disclosed
Hyderabad, Telangana, India
Salary: Not disclosed
Salary: Not disclosed
Hyderabad, Telangana, India
Salary: Not disclosed
