Posted:5 days ago|
Platform:
On-site
Full Time
• Should have experience on block level, IP level and chip level layouts.
• Should have hands-on experience in creating layout of critical blocks such as LDO,ADC,DAC,Bandgap,Buck and boost converters etc..
• Good understanding of analog layout fundamentals such as matching,WPE,STI,LOD,Electromigration,crosstalk,latchup etc..
• Ability to understand design constraints and implement high quality layouts.
• Strong debug and problem solving skills for LVS,DRC,Antenna and EM/IR.
• Multiple tape out support experience will be an added advantage.
• Excellent written and oral communication skills required.
• Proven experience in mentoring and guiding junior engineers.
Best NanoTech
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