AMS Verification Engineer

As an AMS Verification Engineer, you will play a crucial role in verifying Analog Mixed Signal (AMS) designs. Your role overview includes developing and executing verification plans, creating testbenches, maintaining real number models, collaborating with design teams, and verifying IP/chip functionality. Your daily tasks will involve working with RNM modeling, Cadence AMS/DMS flow, SystemVerilog, Verilog-AMS, UVM, and basic scripting/automation. Strong communication and documentation skills are essential for this role. Key Responsibilities: - Develop and execute verification plans for AMS designs. - Create and automate testbenches for AMS verification. - Build and maintain SystemVerilog real number models. - Collaborate with analog and digital design teams to ensure designs meet specifications. - Verify AMS/DMS IP/chip functionality. Qualifications Required: - More than 5 years of experience in AMS verification. - Hands-on RNM modeling exposure. - Proficiency with Cadence AMS/DMS flow. - Strong RNM modeling skills. - Experience with SystemVerilog and Verilog-AMS. - Knowledge of analog and mixed-signal design principles. - Experience with UVM. - Ability to debug AMS modeling issues. - Experience with basic scripting/automation. - Good communication and documentation skills. If you have the above qualifications and are excited to contribute to a dynamic team, we look forward to hearing from you.,