7 Yield Analysis Jobs

You are invited to join our team at Sandisk as a DFT Engineer, where you will play a crucial role in developing the next-generation Flash Controllers. As an SoC DFT Engineer, your primary responsibility will be to define and implement cutting-edge DFT solutions, focusing on SCAN, MBIST, BSDL, and other key aspects. The ideal candidate should possess a profound understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG, and Simulation expertise. As a DFT Engineer at Sandisk, you will be involved in various essential duties and responsibilities, including: - Defining DFT Architecture for SoC development. - Leading complex activities and offering solutions for intricate DFT problems. - Collaborating with cross-functional teams to establish and refine SoC DFT requirements in alignment with industry standards and customer needs. - Working closely with Design, Verification, Physical Design, and Test Engineering teams to guide them on test requirements and methodologies. - Collaborating with the Product Engineering team to comprehend test requirements and participating in complex silicon debugs. - Evaluating all aspects of the SoC DFT flow from requirements to detailed definitions and continuously improving the DFT methodology in collaboration with CAD. Qualifications: - B.Tech / M.Tech / Ph.D. in Electronics, Computer Science, or Electrical Engineering. - Minimum of 15+ years of experience in DFT. - Strong understanding of DFT Architecture. Key Skills: - Extensive experience in SoC DFT architecture, DFT IP development, and DFT methodology. - Proven track record of driving DFT architecture in complex ASIC designs. - Ability to work independently on multiple complex DFT problems across different projects. - Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs). - Proficiency in SCAN, MBIST implementation. - Solid understanding of JTAG & BSDL standards. - Good understanding of Test clocking requirements, Test mode timing closure. - Proficiency in complex silicon debugs and yield analysis. - Solid understanding of SoC architecture and low-power design principles. - Understanding of High-Speed interfaces (PCIe or UFS protocols) and experience with SSD/Flash is an advantage. - Excellent analytical and problem-solving skills. - Strong communication skills and the ability to work effectively in cross-functional teams. At Sandisk, we value diversity and believe that a diverse workforce leads to the best outcomes for our employees, customers, and communities. We are committed to creating an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution. Additionally, we offer opportunities to applicants with disabilities and ensure a smooth navigation of our careers website and hiring process. If you require any accommodations during the application process, please reach out to us at jobs.accommodations@sandisk.com with details of your request, the job title, and requisition number.,

As a highly skilled and experienced leader in MES, you will be responsible for leading the strategy, development, and operation of Manufacturing Execution Systems across all assembly and test operations. Your primary focus will be on semiconductor packaging and testing processes, with a deep understanding of MES solutions and a commitment to continuous improvement in a fast-paced, customer-driven environment. Your key responsibilities will include: - Leading the MES strategy for semiconductor products" assembly and test operations to improve efficiency, quality, and customer satisfaction. - Overseeing MES deployment, configuration, and support across various assembly, package, and test platforms in a high-mix, high-volume environment. - Collaborating with R&D, engineering, and operations teams to ensure seamless integration of the MES system with automated test equipment, robotic handling systems, and packaging tools. - Ensuring real-time data collection, traceability, and quality compliance through the MES system to meet customer-specific requirements. - Managing system integration between MES, ERP (e.g., SAP), PLM, and test data management systems to ensure smooth data flow across the enterprise. - Implementing equipment automation using SECS/GEM and CPIB for auto tracking, data collection, validations, and recipe management. - Implementing Recipe Management System (RMS) in Assembly and Test manufacturing plants. - Collaborating with QA and process engineering teams to drive yield analysis, failure analysis, and continuous improvement using MES data. - Designing and implementing KPIs to measure system performance, on-time delivery, throughput, and quality metrics. - Optimizing MES systems for equipment utilization, test time reduction, and real-time fault detection to meet customer delivery requirements. - Ensuring MES solutions support regulatory compliance and proper data retention for ISO standards and customer-specific audits. - Leading and mentoring a team of MES professionals, supporting their career development and fostering a culture of innovation and continuous improvement. - Implementing Statistical Process Control (SPC) and OEE dashboards for equipment usage effectiveness. - Overseeing vendor management to ensure the MES platform meets the evolving needs of the assembly/test environment and stays current with industry trends. To qualify for this role, you should have: - A Bachelors or Masters degree in Electrical Engineering, Industrial Engineering, Computer Science, or a related field. - 15+ years of experience in semiconductor assembly, test, and packaging with at least 5 years in a leadership role focused on MES within an OSAT or semiconductor manufacturing environment. - Proficiency in semiconductor assembly and testing processes, MES platforms, real-time data acquisition, and data integration with equipment and enterprise systems. - Demonstrated ability to drive yield improvement, cycle time reduction, and cost control through MES initiatives. - Strong leadership, team management, and communication skills. - Preferred qualifications include experience with data analytics tools, test data management, process automation, and customer interaction. In this role, you can expect to work in a fast-paced, dynamic environment with a focus on continuous improvement. You will collaborate across multiple sites with cross-functional teams and occasionally travel to customer sites or external vendors for system integration, audits, or troubleshooting.,

As part of the ASIC modeling team, you will be responsible for developing, maintaining, and testing the NAND/SoC models using C/C++/SystemC. The SoC models aim to accurately capture the functionality of the controller chip that oversees the NAND storage. You should have 4 to 7 years of experience and possess expertise in DFT implementation and verification. Additionally, experience in MBIST implementation and verification, along with a strong grasp of DFT/MBIST fundamentals, is essential. You will be involved in tasks such as DRC Clean up, coverage improvement, and modifying MBIST algorithms. It would be beneficial to have knowledge in PERL/TCL Scripting/Python and using assertions for monitoring clock frequencies and test-related registers. Familiarity with yield analysis and improvement flow, understanding CLP constructs, and working in multi-voltage, multi-power design environments will be advantageous. Your expected roles will include architecting DFT based on the PETE, Design, and Customer specifications. A self-motivated, self-driven attitude with a thirst for learning is desirable for this position. The ideal candidate should hold a BE/Btech/Mtech/ME degree. Western Digital values diversity and believes that embracing various perspectives leads to the best outcomes. The company is dedicated to creating an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution. Western Digital is committed to providing equal opportunities to applicants with disabilities. If you require accommodations during the application process, please contact us at staffingsupport@wdc.com with details of your request, including the job title and requisition number.,

You should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, encompassing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial to have familiarity with ATPG, Low Value (LV), Built-in self-test (BIST), or Joint Test Action Group (JTAG) tool and flow. Ideally, you should also have experience with a programming language like Perl, along with expertise in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA). Proficiency in performance design DFT techniques, understanding of the end-to-end flows in Design, Verification, DFT, and Partner Domains (PD), and the ability to scale DFT would be advantageous. As part of our dynamic team, you will be involved in developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in the innovation of products that are cherished by millions globally. Your skills will influence the next wave of hardware experiences, delivering exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team synergizes the best of Google AI, Software, and Hardware to craft profoundly beneficial experiences. We are dedicated to researching, designing, and advancing new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately striving to enhance people's lives through technology. Your responsibilities will include collaborating with a team dedicated to Design for Testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, Static Timing Analysis (STA) checks. You will be tasked with crafting Pattern delivery using Automatic Test Pattern Generation (ATPG), engaging in Silicon bring-up, working on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug, and delivering debug patterns while conducting Silicon data analysis.,

As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Your key responsibilities will include defining architecture and design specifications for custom memory IPs, optimizing circuits such as memory cell arrays, sense amplifiers, and decoders, leading schematic-level design and simulation, collaborating with layout and verification teams, guiding post-layout activities, ensuring designs meet requirements for DFM and reliability, contributing to methodology development, supporting silicon bring-up, and providing technical leadership to junior engineers. To be successful in this role, you should have a B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering, along with 8+ years of experience in full-custom memory design. You should possess a solid understanding of CMOS analog/digital circuit design principles, expertise in circuit simulation tools, experience with advanced nodes, and hands-on experience with variation analysis, IR drop, and EM checks. Strong analytical, communication, and leadership skills are essential for this position. Preferred qualifications include experience in memory compiler design, knowledge of low-power memory design techniques, experience with ECC and redundancy strategies, familiarity with ISO 26262/Safety compliance, and scripting knowledge for automation of design and simulation flows. If you are interested in this opportunity, please share your CV with Sharmila.b@acldigital.com.,

You are invited to join our team as an SMT/ MLB Failure Analysis Engineer at the position of Asst Manager / Deputy Manager with 10-18 years of experience. The job is based in Hosur. As an SMT / MLB Failure Analysis Engineer, you will be responsible for leading complex failure analysis of MLBs and SMT assemblies using advanced diagnostic tools such as X-ray, SEM, ICT, and AOI. Your role will involve performing root cause analysis on field returns, in-process failures, and customer complaints. You will develop and implement corrective and preventive actions to eliminate recurring issues while collaborating with design, process, and quality teams to enhance product and process robustness. Analyzing yield trends and driving continuous improvement initiatives will be a key part of your responsibilities. Additionally, you will be required to prepare detailed technical reports, present findings to internal and external stakeholders, mentor junior engineers and technicians in failure analysis methodologies and tools, and ensure documentation compliance with industry standards such as IPC, ISO, and IATF. To excel in this role, you should possess a Bachelors or Masters degree in Electronics, Electrical Engineering, or a related field along with 10-15 years of hands-on experience in failure analysis within the EMS industry. Your strong knowledge of SMT processes, PCB design, and component-level diagnostics will be essential. Proficiency in tools like oscilloscopes, multimeters, X-ray, SEM, FIB, and thermal imaging is required. Familiarity with IPC standards (IPC-A-610, IPC-7711/7721) and quality systems such as ISO 9001 and IATF 16949 will be advantageous. Excellent analytical, documentation, and communication skills are also crucial for success in this role. If you are seeking a challenging opportunity to apply your expertise in failure analysis and contribute to continuous improvement efforts in a dynamic environment, we encourage you to apply for this position. We look forward to welcoming you to our team. Best Regards, Team HR,

As a candidate for the role, you should possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or have equivalent practical experience. Additionally, you need to have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, including managing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial that you have familiarity with ATPG, Low Value (LV), Built-in Self Test (BIST), or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications for this position include proficiency in a programming language such as Perl, along with experience in Synthesis, Lint, Change Data Capture (CDC), Local Enhanced Content (LEC), DFT timing, and Static Timing Analysis (STA). An understanding of performance design DFT techniques, end-to-end flows in Design, Verification, DFT, and Partner Domains (PD), as well as the ability to scale DFT will be advantageous. Joining our team means being part of a group that continually pushes boundaries, focusing on developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in the innovation that underpins products adored by millions globally. Your expertise will be instrumental in shaping the next wave of hardware experiences, delivering unmatched performance, efficiency, and integration. At Google, our mission is to organize the world's information and make it universally accessible and useful. Our collaborative team leverages the best of Google AI, Software, and Hardware to create exceptionally helpful experiences. We are dedicated to researching, designing, and developing new technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to enhance people's lives through technology. In this role, your responsibilities will include collaborating with a team focusing on Design for testing (DFT) verification, Pattern generation, Standard Delay Format (SDF) simulations, and Static Timing Analysis (STA) checks. You will be tasked with writing a Pattern delivery using Automatic Test Pattern Generation (ATPG), contributing to Silicon bring-up, working on Yield, Vmin or Return Materials/Merchandise Authorization (RMA) debug, and delivering debug patterns, as well as performing Silicon data analysis.,