13 Yield Analysis Jobs

As a qualified circuit designer, you will be working on the next generation analog & mixed-signal (AMS) circuits for world-leading systems-on-chip (SOCs). You will be an essential part of a growing AMS team focused on design and productization using leading-edge CMOS process technology nodes. - Perform transistor-level feasibility study and modeling for various analog/mixed-signal circuit blocks - Design blocks and document design simulations and verifications towards formal design reviews - Drive mask design to implement layout views of designs and participate in layout reviews - Conduct post-layout and top-level simulations to validate top-level integration - Run design verification flows ...

As a Post Silicon Validation Engineer or ATE Engineer based in Bangalore with 5 days office mode and less than 30 days notice period, your role involves the following responsibilities: - Strong expertise in ATE systems, including Advantest 93K/ V 93K/HDMT, is a must. - Demonstrated proficiency in programming languages such as Python, C/C++, and x86 Assembly. - In-depth understanding of the semiconductor manufacturing product life cycle. - Knowledge of hardware design concepts like load boards and probe cards. - Familiarity with data extraction and analysis tools like JMP and Aqua. - Ability to develop and debug test programs to ensure accurate results, participate in yield analysis, and set ...

As a DFT Technical Manager at NextSilicon, you will play a crucial role in the DFT implementation of the company's next SOC. Your primary focus will be on developing and implementing testing methodologies to ensure the functionality, reliability, and manufacturability of integrated circuits (ICs) and other hardware designs. Your responsibilities will include developing DFT flow/methodologies, managing a team of 3-4 DFT engineers, and ensuring thorough testing and fault coverage alignment with industry standards. **Role Overview:** NextSilicon is reimagining high-performance computing with accelerated compute solutions and a software-defined hardware architecture. As a DFT Technical Manager, ...

Role & responsibilities -Heading costing department of HO and Plants -Production cost with variance analysis as compared to standard -Batch Costing -Job Costing -Overhead reports -Yield analysis

Role Overview: As a member of the Tata Electronics Pvt. Ltd. team, your role will involve overseeing various key aspects related to DoE review, process review, process planning, and escalations. You will be responsible for ensuring effective planning, execution, and validation of Design of Experiments (DOEs), as well as verifying the implementation of process changes and conducting stack-up analysis. Additionally, you will play a crucial role in planning and coordinating development schedules, risk assessments, and mitigation plans to meet customer requirements and development timelines. Your role will also involve handling escalations and ensuring timely resolution of issues that may arise ...

As a Quality Engineer at IRP Systems, you will play a crucial role in the development of high-performance e-powertrain systems that are set to revolutionize the electric vehicles market. We are looking for an experienced professional to join our team in India. Your responsibilities will include: - Building, managing, monitoring, and implementing Suppliers" quality plans and assessing their quality performance. - Conducting visits and audits at suppliers" sites to address questionnaires, FAI, and any managerial concerns. - Executing Supplier quality procedures, CAPA, SCAR & 8D, and preparing quality reports. - Leading the EMS quality activities to ensure compliance with IRP requirements. - Ov...

You are invited to join our team at Sandisk as a DFT Engineer, where you will play a crucial role in developing the next-generation Flash Controllers. As an SoC DFT Engineer, your primary responsibility will be to define and implement cutting-edge DFT solutions, focusing on SCAN, MBIST, BSDL, and other key aspects. The ideal candidate should possess a profound understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG, and Simulation expertise. As a DFT Engineer at Sandisk, you will be involved in various essential duties and responsibilities, including: - Defining DFT Architecture for SoC development. - Leading complex activities and offering solutions for intricate DFT proble...

As a highly skilled and experienced leader in MES, you will be responsible for leading the strategy, development, and operation of Manufacturing Execution Systems across all assembly and test operations. Your primary focus will be on semiconductor packaging and testing processes, with a deep understanding of MES solutions and a commitment to continuous improvement in a fast-paced, customer-driven environment. Your key responsibilities will include: - Leading the MES strategy for semiconductor products" assembly and test operations to improve efficiency, quality, and customer satisfaction. - Overseeing MES deployment, configuration, and support across various assembly, package, and test platf...

As part of the ASIC modeling team, you will be responsible for developing, maintaining, and testing the NAND/SoC models using C/C++/SystemC. The SoC models aim to accurately capture the functionality of the controller chip that oversees the NAND storage. You should have 4 to 7 years of experience and possess expertise in DFT implementation and verification. Additionally, experience in MBIST implementation and verification, along with a strong grasp of DFT/MBIST fundamentals, is essential. You will be involved in tasks such as DRC Clean up, coverage improvement, and modifying MBIST algorithms. It would be beneficial to have knowledge in PERL/TCL Scripting/Python and using assertions for monit...

You should hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, encompassing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial to have familiarity with ATPG, Low Value (LV), Built-in self-test (BIST), or Joint Test Action Group (JTAG) tool and flow. Ideally, you should also have experience with a programming language like Perl, along with expertise in Synthesis, Lint, Change Data Capture ...

As a Lead Memory Design Engineer, you will be responsible for driving the architecture, design, and development of advanced memory IPs including SRAMs, ROMs, CAMs, and Register Files. Your role will involve leading a team of designers, collaborating with cross-functional groups, and delivering high-performance, low-power, and silicon-proven memory solutions at advanced technology nodes. Your key responsibilities will include defining architecture and design specifications for custom memory IPs, optimizing circuits such as memory cell arrays, sense amplifiers, and decoders, leading schematic-level design and simulation, collaborating with layout and verification teams, guiding post-layout act...

You are invited to join our team as an SMT/ MLB Failure Analysis Engineer at the position of Asst Manager / Deputy Manager with 10-18 years of experience. The job is based in Hosur. As an SMT / MLB Failure Analysis Engineer, you will be responsible for leading complex failure analysis of MLBs and SMT assemblies using advanced diagnostic tools such as X-ray, SEM, ICT, and AOI. Your role will involve performing root cause analysis on field returns, in-process failures, and customer complaints. You will develop and implement corrective and preventive actions to eliminate recurring issues while collaborating with design, process, and quality teams to enhance product and process robustness. Analy...

As a candidate for the role, you should possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or have equivalent practical experience. Additionally, you need to have at least 5 years of experience in Application-Specific Integrated Circuit (ASIC) design for test, including managing the silicon life cycle through DFT pattern bring-up on Automatic Test Equipment (ATE) and manufacturing. It is crucial that you have familiarity with ATPG, Low Value (LV), Built-in Self Test (BIST), or Joint Test Action Group (JTAG) tool and flow. Preferred qualifications for this position include proficiency in a programming language such as Pe...