317 Xilinx Jobs - Page 9

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role AMD is looking for a senior software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD’s abilities to deliver the highest quality, industry-leading technologies to market. The Person The ideal candidate possesses an innovative and problem-solving mindset, has a keen eye for Software engineering development, and is diligent and passionate about Technology. A successful candidate will need to employ strong knowledge in computer technologies, leadership skills in technical areas, and SW engineering expertise as well as a strong ability to compete effectively in a fast-paced, relevant environment while working with different teams of engineers and collaborators. Key Responsibilities Develop and drive execution of comprehensive, highly effective software for sophisticated new technology and new product introduction projects Validate new SW features before releasing them to customers Contribute to a high-functioning feature team Collaborate closely with multiple teams to deliver key planning solutions and the technology to support them Help contribute to the design and implementation of future architecture for a highly scalable, durable, and innovative system Work very closely with dev teams and Project Managers to drive results Preferred Experience Strong digital design and simulations basics RTL (VHDL, Verilog & System Verilog) coding skills Understanding of FPGA design flow and tools (Synthesis, Simulation and implementation) ASIC/FPGA verification experience - VHDL and Verilog Xilinx Vivado Design Suite experience Hands on experience on simulators like XSIM, Questa, Modelsim, VCS etc. Advanced Debug skills in software environment or strong problem-solving skills Hands on experience with scripting preferably tcl, pearl and python Academic Credentials Bachelor’s or Master’s degree in Computer/Software Engineering, Computer Science, or related technical discipline Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Min 10 yrs of R&D experience in FPGA development (Altera, Xilinx) Experience of RTL languages - VHDL or Verilog Xilinx FPGA Tools Design Flow - Vivado, Chipscope, Quartus. EDA Functional Simulation tools – Synopsys or Mentor or Cadence.

Job Title: FPGA Architect Location: Gurgoan, HR Experience: 10+ Years Job Summary: As FPGA Architect, you will lead the design development effort on a variety of projects in a highly collaborative, fast-paced environment. In this role, you will be responsible for the definition and development of complex FPGA designs for our Test products. You will work closely with RD Project Manager, Product Architects, Solution Teams, FPGA developers, Software Qualification and Software Engineers to develop new product offerings and improve existing ones. The candidate should be a strong team worker and should be able and willing to collaborate with other design teams located in US Europe. Qualifications Essential: Bachelor degree or masters degree in electrical / Electronic Engineering Minimum 10 years of RD experience in FPGA development (Altera, Xilinx) Experience of RTL languages - VHDL or Verilog Experience of Xilinx FPGA Tools Design Flow - Vivado, Chipscope, Quartus. Experience of EDA Functional Simulation tools Synopsys or Mentor or Cadence Experience of Altera or Xilinx FPGA Tools Design Flow Ability to quickly learn new technologies, protocols and product segments Experience of creating self-checking Simulation environment involving test bench, scripts for automation, writing test cases. Collaborate with system architects to define the system architecture and determine how the FPGA will interface with other components on the PCA board and choose an appropriate FPGA based on the projects requirements. Experience with timing closure for complex designs Excellent written skills which are required for creating documents like Product Definition, Detailed FPGA Design, Hardware Software Interface documents Self-motivated and self-organized Excellent team-player, responsive and accountable Excellent verbal communication skills Preferred: Experience with Keysight instruments like Oscilloscope, Analyzer, AWG BERT Experience of working on Protocols such as PCI Express, USB, MIPI (MPHY, DPHY, CPHY based), Ethernet, DDR etc. Experience in international collaboration (US EUR) Experience in multi-vendor collaboration (software supplied by and/or to external organizations)

JOB DESCRIPTION As FPGA Architect , you will lead the design & development effort on a variety of projects in a highly collaborative, fast-paced environment. In this role, you will be responsible for the definition and development of complex FPGA designs for our Test products. You will work closely with R&D Project Manager, Product Architects, Solution Teams, FPGA developers, Software Qualification and Software Engineers to develop new product offerings and improve existing ones. The candidate should be a strong team worker and should be able and willing to collaborate with other design teams located in US & Europe. Qualifications Essential: Bachelor degree or Master's degree in electrical / Electronic Engineering Minimum 10 years of R&D experience in FPGA development (Altera, Xilinx) Experience of RTL languages - VHDL or Verilog Experience of Xilinx FPGA Tools Design Flow - Vivado, Chipscope, Quartus. Experience of EDA Functional Simulation tools – Synopsys or Mentor or Cadence Experience of Altera or Xilinx FPGA Tools Design Flow Ability to quickly learn new technologies, protocols and product segments Experience of creating self-checking Simulation environment involving test bench, scripts for automation, writing test cases. Collaborate with system architects to define the system architecture and determine how the FPGA will interface with other components on the PCA board and choose an appropriate FPGA based on the project's requirements. Experience with timing closure for complex designs Excellent written skills which are required for creating documents like Product Definition, Detailed FPGA Design, Hardware & Software Interface documents Self-motivated and self-organized Excellent team-player, responsive and accountable Excellent verbal communication skills Preferred: Experience with Keysight instruments like Oscilloscope, Analyzer, AWG & BERT Experience of working on Protocols such as PCI Express, USB, MIPI (MPHY, DPHY, CPHY based), Ethernet, DDR etc. Experience in international collaboration (US & EUR) Experience in multi-vendor collaboration (software supplied by and/or to external organizations) Job Type: Full-time Pay: ₹2,000,000.00 - ₹2,500,000.00 per month Benefits: Flexible schedule Work Location: In person

Ubuntu Linux, already the most popular Linux distribution in the world, is looking to increase its adoption even further by expanding the number of System On Chip (SoC) platforms supported natively and further optimising to ensure the highest performant experience for all users. There is a strong demand from silicon manufacturers such as NVIDIA, Xilinx, MediaTek, and Qualcomm to provide Ubuntu Linux to their customers and Canonical is looking to broaden its silicon enablement squads to meet this challenge. The Canonical Kernel Team - those responsible for the build, maintenance, and distribution of the Linux kernel for Ubuntu - are looking for individuals with a strong flair for software development at the hardware level and a passion for ensuring the most optimal performance the silicon can provide. The successful candidate will be able to prove a strong aptitude for software engineering at the hardware level. While direct experience with the Linux kernel would be a substantial advantage, it is not a hard requirement for candidates with prior background in other RTOS' or bare-metal environments as long as direct hardware experience can be demonstrated. There are a number of work-from-home based roles available worldwide and we are looking for experience levels from early career candidates with a couple of years under their belt up through senior industry veterans. What your day will look like Collaborate regularly and proactively with a globally distributed team Work closely with our silicon vendor partners to integrate their platform support into the Ubuntu Linux kernel for their product ranges Diagnose and resolve issues in the kernel reported by partners, customers, the community at large, and discovered by your own rigorous testing Take responsibility for the delivery of distinct silicon-optimised variants of the Ubuntu Linux kernel to the world Improve tooling and automation for the delivery and test of Ubuntu Linux kernels Submit, review, and apply kernel patches, working with both internal and external upstream maintainers Identify new means of maximising performance on partner silicon What we are looking for in you Well-organised and motivated self-starter able to thrive in a remote work environment Professional manner with colleagues, business partners, and the open-source community Ability to communicate effectively in English, both written and verbal Significant programming ability in C Strong grasp of device drivers, BSP's, and other aspects of hardware-level system engineering Solid background with git Understanding of operating system kernel fundamentals Ability to travel twice a year for company events of up to two weeks length Additional skills that you might also bring Python and Bash scripting ability Prior background with the major SoC families Ubuntu/Debian/Snap packaging Demonstrated experience with Linux kernel patching and debugging Solid understanding of performance optimisation for silicon platforms What we offer you We consider geographical location, experience, and performance in shaping compensation worldwide. We revisit compensation annually to ensure we recognise outstanding performance. In addition to base pay, we offer a performance-driven annual bonus. We provide all team members with additional benefits, which reflect our values and ideals. We balance our programs to meet local needs and ensure fairness globally. Home-based work environment with twice-yearly team sprints in person Personal learning and development budget of USD 2,000 per year Annual compensation review Recognition rewards Annual holiday leave Maternity and paternity leave Employee Assistance Programme Opportunity to travel to new locations to meet colleagues Priority Pass, and travel upgrades for long haul company events About Canonical Canonical is a pioneering tech firm at the forefront of the global move to open source. As the company that publishes Ubuntu, one of the most important open source projects and the platform for AI, IoT and the cloud, we are changing the world on a daily basis. We recruit on a global basis and set a very high standard for people joining the company. We expect excellence - in order to succeed, we need to be the best at what we do. Canonical has been a remote-first company since its inception in 2004. Working here is a step into the future, and will challenge you to think differently, work smarter, learn new skills, and raise your game. Canonical is an equal opportunity employer We are proud to foster a workplace free from discrimination. Diversity of experience, perspectives, and background create a better work environment and better products. Whatever your identity, we will give your application fair consideration.

Ubuntu Linux, already the most popular Linux distribution in the world, is looking to increase its adoption even further by expanding the number of System On Chip (SoC) platforms supported natively and further optimising to ensure the highest performant experience for all users. There is a strong demand from silicon manufacturers such as NVIDIA, Xilinx, MediaTek, and Qualcomm to provide Ubuntu Linux to their customers and Canonical is looking to broaden its silicon enablement squads to meet this challenge. The Canonical Kernel Team - those responsible for the build, maintenance, and distribution of the Linux kernel for Ubuntu - are looking for individuals with a strong flair for software development at the hardware level and a passion for ensuring the most optimal performance the silicon can provide. The successful candidate will be able to prove a strong aptitude for software engineering at the hardware level. While direct experience with the Linux kernel would be a substantial advantage, it is not a hard requirement for candidates with prior background in other RTOS' or bare-metal environments as long as direct hardware experience can be demonstrated. There are a number of work-from-home based roles available worldwide and we are looking for experience levels from early career candidates with a couple of years under their belt up through senior industry veterans. What your day will look like Collaborate regularly and proactively with a globally distributed team Work closely with our silicon vendor partners to integrate their platform support into the Ubuntu Linux kernel for their product ranges Diagnose and resolve issues in the kernel reported by partners, customers, the community at large, and discovered by your own rigorous testing Take responsibility for the delivery of distinct silicon-optimised variants of the Ubuntu Linux kernel to the world Improve tooling and automation for the delivery and test of Ubuntu Linux kernels Submit, review, and apply kernel patches, working with both internal and external upstream maintainers Identify new means of maximising performance on partner silicon What we are looking for in you Well-organised and motivated self-starter able to thrive in a remote work environment Professional manner with colleagues, business partners, and the open-source community Ability to communicate effectively in English, both written and verbal Significant programming ability in C Strong grasp of device drivers, BSP's, and other aspects of hardware-level system engineering Solid background with git Understanding of operating system kernel fundamentals Ability to travel twice a year for company events of up to two weeks length Additional skills that you might also bring Python and Bash scripting ability Prior background with the major SoC families Ubuntu/Debian/Snap packaging Demonstrated experience with Linux kernel patching and debugging Solid understanding of performance optimisation for silicon platforms What we offer you We consider geographical location, experience, and performance in shaping compensation worldwide. We revisit compensation annually to ensure we recognise outstanding performance. In addition to base pay, we offer a performance-driven annual bonus. We provide all team members with additional benefits, which reflect our values and ideals. We balance our programs to meet local needs and ensure fairness globally. Home-based work environment with twice-yearly team sprints in person Personal learning and development budget of USD 2,000 per year Annual compensation review Recognition rewards Annual holiday leave Maternity and paternity leave Employee Assistance Programme Opportunity to travel to new locations to meet colleagues Priority Pass, and travel upgrades for long haul company events About Canonical Canonical is a pioneering tech firm at the forefront of the global move to open source. As the company that publishes Ubuntu, one of the most important open source projects and the platform for AI, IoT and the cloud, we are changing the world on a daily basis. We recruit on a global basis and set a very high standard for people joining the company. We expect excellence - in order to succeed, we need to be the best at what we do. Canonical has been a remote-first company since its inception in 2004. Working here is a step into the future, and will challenge you to think differently, work smarter, learn new skills, and raise your game. Canonical is an equal opportunity employer We are proud to foster a workplace free from discrimination. Diversity of experience, perspectives, and background create a better work environment and better products. Whatever your identity, we will give your application fair consideration.

Role: Hardware Engineer Location: Hyderabad and Bangalore Experience : 3- 8 yrs Role & responsibilities Should have experience in Aerospace Industry. High speed Mixed Signal Design Expertise (FPGA, SoC, MPSoC, RFSoC, Versal). Knowledge in designing of power Modules (Regulators, Switchers, DC-DC convertors, etc). Understanding of schematic design in Orcad/Altium. Hands on experience in Design and debug on interfaces such as I2C, UART, SPI, AFDX, Ethernet, 1553 etc. Knowledge in memories Like Nand Flash, Nor Flash, SD-Ram(DDR), EEprom, NVSram,emmc. Knowledge in Circuit design, circuit simulation, calculation and analysis of circuit(SI, PI, Derating, MTBF ). Documentation. Good communication skills & Interaction with Clients/ Inspection agency.

This requirement is for design and development for candidates with experience and working knowledge of latest AMD/Xilinx FPGAs/SoC/Versal/Alveo/RFSoC devices Responsibilities Candidate will be responsible for firmware coding, hardware implementation using VHDL/Verilog/Python/C/C++. Candidate will be responsible for embedded system design, digital readout system designs, ADC/DAC interfacing, High Speed RF design and AI/ML implementation on FPGA platform development. Qualifications BTech / MTech in Electronics / VLSI / Embedded Systems / Computer Science Minimum 3+ experience in FPGA design and development is mandatory. Only core experience will be considered. Freshers will not be considered. Practical Exposure to FPGA design is mandatory Must have at least one strong skill out of the ones listed under "responsibilities" Must be self driven with strong analytical skills and must be a quick learner Must have good communication skills Must be hard working and focused

Job Description: Understand customers requirements /specifications /tender enquiry. Define DSP, System and Board architecture. Project ownership from concept to delivery. This includes identifying risks, dependencies, creating mitigation plan, tracking project schedule, discussions with customers, design reviews. Partition the algorithms for implementing in FPGA and/or in SW. Identify the building blocks & Signal Processing functions. Provide estimates on FPGA resources, computation bandwidth, and memory bandwidth. Create module level details from architecture, coding, simulation and perform peer reviews. Apply the methodologies for design, verification or validation. Define, create and maintain all project related documentation, especially design documents with detailed analysis reports. Provide support to customer during integration phases at test sites and support to production teams. Defining the architecture of RTL functions HDL Coding Simulation and Implementation Testing on board and debugging Professional Skills: VHDL Knowledge Xilinx tools for synthesis and implementation Thorough understanding of Xilinx FPGAs Functional Simulation Hardware Design : Logic Design & Debugging expertise FPGA Design : VHDL/Verilog RTL Coding, System C/ System Verilog FPGA Synthesis & PAR Tools Implementing DSP algorithms in FPGA environment for Radar and Electronic Warfare systems. Modeling the algorithms in Octave/MATLAB, generating test vectors, visualizing data. Working knowledge on interfacing with ADCs and DACs and interpreting their performance. Fluency, good communication & presentation skills. Configuration/Version control tools like SVN

Role Purpose The purpose of the role is to support process delivery by ensuring daily performance of the Production Specialists, resolve technical escalations and develop technical capability within the Production Specialists. Do Oversee and support process by reviewing daily transactions on performance parameters Review performance dashboard and the scores for the team Support the team in improving performance parameters by providing technical support and process guidance Record, track, and document all queries received, problem-solving steps taken and total successful and unsuccessful resolutions Ensure standard processes and procedures are followed to resolve all client queries Resolve client queries as per the SLAs defined in the contract Develop understanding of process/ product for the team members to facilitate better client interaction and troubleshooting Document and analyze call logs to spot most occurring trends to prevent future problems Identify red flags and escalate serious client issues to Team leader in cases of untimely resolution Ensure all product information and disclosures are given to clients before and after the call/email requests Avoids legal challenges by monitoring compliance with service agreements Handle technical escalations through effective diagnosis and troubleshooting of client queries Manage and resolve technical roadblocks/ escalations as per SLA and quality requirements If unable to resolve the issues, timely escalate the issues to TA & SES Provide product support and resolution to clients by performing a question diagnosis while guiding users through step-by-step solutions Troubleshoot all client queries in a user-friendly, courteous and professional manner Offer alternative solutions to clients (where appropriate) with the objective of retaining customers and clients business Organize ideas and effectively communicate oral messages appropriate to listeners and situations Follow up and make scheduled call backs to customers to record feedback and ensure compliance to contract SLAs Build people capability to ensure operational excellence and maintain superior customer service levels of the existing account/client Mentor and guide Production Specialists on improving technical knowledge Collate trainings to be conducted as triage to bridge the skill gaps identified through interviews with the Production Specialist Develop and conduct trainings (Triages) within products for production specialist as per target Inform client about the triages being conducted Undertake product trainings to stay current with product features, changes and updates Enroll in product specific and any other trainings per client requirements/recommendations Identify and document most common problems and recommend appropriate resolutions to the team Update job knowledge by participating in self learning opportunities and maintaining personal networks Deliver NoPerformance ParameterMeasure1ProcessNo. of cases resolved per day, compliance to process and quality standards, meeting process level SLAs, Pulse score, Customer feedback, NSAT/ ESAT2Team ManagementProductivity, efficiency, absenteeism3Capability developmentTriages completed, Technical Test performance Mandatory Skills: FPGA Design. Experience5-8 Years.

What is Armory? What we are building requires hard work, tenacity, ownership, creativity and way more man-hours than an everyday job. If you are a savant at what you do, love autonomy, have high agency and genuinely want to impact the future of this country, we want you to work with us starting yesterday! Modern conflicts waged remotely demand a radical rethinking of strategy as adversaries deploy inexpensive drones and technology to inflict maximum damage with minimal risk. If you prefer routine over the dynamic unpredictability of innovation, Armory isn't for you. Our fast-paced environment requires genuine curiosity, resilience, a passion for continuous learning, and comfort with rapid change. Armory is a new age defence tech startup building next-generation products to strengthen Indian forces in the modern battlefields. About the founder Amardeep Singh is an IIT Bombay alumnus & an aerospace engineer by education. He was a founding member of ideaForge - currently India’s biggest drone company & the first drone company to get listed on the Indian stock exchange. His 16-year entrepreneurial journey is marked by a series of ambitious ventures spanning across diverse tech domains like Drones, Consumer Hardware, B2B SaaS & AI. About this role You will be responsible for designing, implementing, and optimizing DSP algorithms and firmware for our state-of-the-art RF products and radar systems. Develop and implement real-time DSP algorithms for radar signal processing, including pulse compression, micro-Doppler processing, and target detection. Work with Software Defined Radios (SDRs), including RFSoC, to optimize signal acquisition and processing. Design and optimize firmware for radar data acquisition, processing, and control. Collaborate with cross-functional teams, including RF engineers and software developers, to integrate DSP firmware into the RF hardware system. Perform tests and troubleshoot RF system to ensure functionality and compliance with regulatory standards. Stay up-to-date with the latest trends and advancements in RF technology. Must haves Min. 15 years of experience in developing DSP algorithms and firmware, with a strong focus on Signal Intelligence (SigInt) applications. Hands-on experience with COMINT and ELINT signal processing. Experience with Software Defined Radios (SDRs) and RFSoC-based implementations. Strong understanding of radar signal processing concepts, including Pulse compression, Doppler processing, Beam-forming, Angle of Arrival/Estimation, DOA, MIMO & CFARs. Experience with communication protocols such as OFDM, QAM, and radar signal processing. Proficiency in programming languages such as C/C++, Python and MATLAB, with experience in developing real-time embedded firmware. Proficiency in working with DSP processors (TI, ADI, Xilinx, or equivalent). Strong debugging skills using lab instruments (oscilloscopes, spectrum analysers, logic analysers). Strong communication and collaboration abilities. Bonus points for Experience in designing and optimizing radar system FMCW chirps. Knowledge of radar architectures, including pulsed, CW, and FMCW radars. Experience with specific radar architectures, such as synthetic aperture radar (SAR) or phased array radar. Knowledge of radar performance metrics and analysis techniques, such as signal-to-noise ratio (SNR), probability of detection, and false alarm rate. Familiarity with radar performance metrics, such as range resolution, Doppler resolution, and sensitivity. Familiarity with radar system simulation tools, such as MATLAB Simulink or SystemVue. Experience with hardware-in-the-loop (HIL) testing and validation of radar systems. Kindly avoid "easy apply" and use the link below to apply: https://armoryshield.zohorecruit.in/jobs/Careers/128390000000334295/RF-Digital-Signal-Processing-Engineer?source=CareerSite

Ubuntu Linux, already the most popular Linux distribution in the world, is looking to increase its adoption even further by expanding the number of System On Chip (SoC) platforms supported natively and further optimising to ensure the highest performant experience for all users. There is a strong demand from silicon manufacturers such as NVIDIA, Xilinx, MediaTek, and Qualcomm to provide Ubuntu Linux to their customers and Canonical is looking to broaden its silicon enablement squads to meet this challenge. The Canonical Kernel Team - those responsible for the build, maintenance, and distribution of the Linux kernel for Ubuntu - are looking for individuals with a strong flair for software development at the hardware level and a passion for ensuring the most optimal performance the silicon can provide. The successful candidate will be able to prove a strong aptitude for software engineering at the hardware level. While direct experience with the Linux kernel would be a substantial advantage, it is not a hard requirement for candidates with prior background in other RTOS' or bare-metal environments as long as direct hardware experience can be demonstrated. There are a number of work-from-home based roles available worldwide and we are looking for experience levels from early career candidates with a couple of years under their belt up through senior industry veterans. What your day will look like Collaborate regularly and proactively with a globally distributed team Work closely with our silicon vendor partners to integrate their platform support into the Ubuntu Linux kernel for their product ranges Diagnose and resolve issues in the kernel reported by partners, customers, the community at large, and discovered by your own rigorous testing Take responsibility for the delivery of distinct silicon-optimised variants of the Ubuntu Linux kernel to the world Improve tooling and automation for the delivery and test of Ubuntu Linux kernels Submit, review, and apply kernel patches, working with both internal and external upstream maintainers Identify new means of maximising performance on partner silicon What we are looking for in you Well-organised and motivated self-starter able to thrive in a remote work environment Professional manner with colleagues, business partners, and the open-source community Ability to communicate effectively in English, both written and verbal Significant programming ability in C Strong grasp of device drivers, BSP's, and other aspects of hardware-level system engineering Solid background with git Understanding of operating system kernel fundamentals Ability to travel twice a year for company events of up to two weeks length Additional skills that you might also bring Python and Bash scripting ability Prior background with the major SoC families Ubuntu/Debian/Snap packaging Demonstrated experience with Linux kernel patching and debugging Solid understanding of performance optimisation for silicon platforms What we offer you We consider geographical location, experience, and performance in shaping compensation worldwide. We revisit compensation annually to ensure we recognise outstanding performance. In addition to base pay, we offer a performance-driven annual bonus. We provide all team members with additional benefits, which reflect our values and ideals. We balance our programs to meet local needs and ensure fairness globally. Home-based work environment with twice-yearly team sprints in person Personal learning and development budget of USD 2,000 per year Annual compensation review Recognition rewards Annual holiday leave Maternity and paternity leave Employee Assistance Programme Opportunity to travel to new locations to meet colleagues Priority Pass, and travel upgrades for long haul company events About Canonical Canonical is a pioneering tech firm at the forefront of the global move to open source. As the company that publishes Ubuntu, one of the most important open source projects and the platform for AI, IoT and the cloud, we are changing the world on a daily basis. We recruit on a global basis and set a very high standard for people joining the company. We expect excellence - in order to succeed, we need to be the best at what we do. Canonical has been a remote-first company since its inception in 2004. Working here is a step into the future, and will challenge you to think differently, work smarter, learn new skills, and raise your game. Canonical is an equal opportunity employer We are proud to foster a workplace free from discrimination. Diversity of experience, perspectives, and background create a better work environment and better products. Whatever your identity, we will give your application fair consideration.

Job description The selected candidate will be responsible for implementing control functions (telemetry and telecommand processing and associated coarse-time functions) in the application of different subsystems in state-of-the-art spaceborne payloads for high-performance applications in indigenous private-sector satellites in India. The work typically may involve, but not necessarily be limited to, the following activities: Understanding control, telemetry and telecommand requirements in operating payloads in orbit and implementing them at subsystem level Evolving efficient firmware architectures and coding for required performance goals in C/C++ Be a team contributor, code for parts of a larger functionality especially seamless integration with high-speed FPGA hardware and test the integrated firmware for requisite performance Part take in the full development cycle and not just design or verification , and be responsible for subsystem level outcome in an integrated system Prepare documents necessary at different stages and be able to interact with QA/QC guidelines and facilitate assurance of code compliance to a given standard including subsystem ICDs As a general rule, Azista requires that all engineers take an enthusiastic part in whatever activity they are required to contribute to in order to make the missions and the company successful. Abilities Required: The knowledge base required in the candidate will in general be a clear understanding of the fundamentals of Expert level sequential coding ability (C/C++) for the embedded environment, a significant experience profile in doing this. Excellent familiarity with the latest microcontroller architectures and a highly desirable experience in instantiating either processor soft cores or the use of hard cores provided in FPGAs Good knowledge and understanding of microcontroller peripheral interfacing standards like UART, SPI, I2C, CAN, SPACEWIRE etc Some desirable knowledge of the architectures of modern high-density FPGAs and SoC Devices from Xilinx (Now AMD) or Actel (Now Microchip) FPGAs Very good experience in actually porting developed code into the hardware platforms and testing the same for target performance characteristics, and the skill in spotting problems and be able to relate observations in tests back to necessary refinements in code Exposure to safe coding practices and high-reliability engineering Qualification: The successful candidate is likely to have An electronics degree, masters preferred but not necessary A consistent career in microcontroller firmware design and coding (6 to 10 years at least) Very good C/C++ Coding skills, knowledge of coding standards and practices Good experience in debugging systems, including the ability to probe hardware and make sense of the observations A good knowledge of hardware concepts and basic circuit theory Note: Interviews are likely to be multi-level very detailed. Please who do not check most of the points above may not be suitable at all. Experience: A consistent career in microcontroller firmware design and coding (6 to 10 years at least) Apply for a Microcontroller Firmware Designer Position Full name Contact number Email address Qualification Working experience

The selected candidate will be responsible for implementing high speed high volume data processing requirements on high density FPGA based hardware. These subsystems are the hearts of satellites and store data gathered on the eternal sojourns of satellites in orbits and send the data down interactively with ground commands. Azista is engaged in the making of state-of-the-art spaceborne payloads for high performance applications in indigenous private sector satellites in India. The work typically may involve, but not necessarily be limited to, the following activities: Understanding onboard image data processing, encryption and packetization (CCSDS) needs and the nuances of indexing, annotating, and storing data and evolving efficient architectures for implementing such functions in FPGA code. Be responsible for coding the above functionalities, porting the successful code and complete the in-situ validation process for the subsystems for flight readiness Be a team contributor, code for parts of a larger functionality and seamless integrate and test the integrated firmware Partake in the full development cycle and not just design or verification, and be responsible for subsystem level outcome in an integrated system Prepare documents necessary at different stages and be able to interact with QA/QC guidelines and facilitate assurance of code compliance to a given standard As a general rule, Azista requires that all engineers take enthusiastic part in whatever activity they are required to contribute to in order to make the missions and the company successful. The knowledge base required in the candidate will in general be a clear understanding of the fundamentals of Coding for FPGA environment, a significant experience profile of doing this. Excellent familiarity and skill in VHDL (or Verilog) and with MATLAB, and porting from it Knowledge of the architectures of modern high-density FPGAs and SoC Devices from Xilinx (Now AMD) or Actel (Now Microchip) FPGAs and familiarity with the use of these Excellent familiarity with the development environments for these devices and the simulation and pre-burn performance validation tools Very good experience of actually porting developed code into the hardware platforms and test the same for target performance characteristics, and the skill in spotting problems and be able to relate observations in tests back to necessary refinements in code Exposure to safe coding practices and high reliability engineering Specific successful design experience with at least two of the following: Encryption, AES standards; desirable exposure to custom encryption with significantly longer keys Data compression techniques, especially image data CCSDS standards for data handling The successful candidate is likely to have An electronics degree, masters preferred but not necessary A consistent career in FPGA based firmware design and coding (6 to 10 years at least) with exposure to high density Xilinx (Now AMD) or Actel (Now Microchip) FPGAs with many designs turned out successfully in high volume data handling including Encryption/Compression/CCSDS etc Good experience in debugging systems, including the ability to probe hardware and make sense of the time domain / frequency domain observations A good knowledge of how to estimate rough-order-of-magnitude power consumption figures of FPGA designs even before a full design is evolved Note: Interviews are likely to be multi-level very detailed. Please who do not check most of the points above may not be suitable at all. A consistent career in FPGA based firmware design and coding (6 to 10 years at least) with exposure to high density Xilinx (Now AMD) or Actel (Now Microchip) FPGAs FPGA Firmware Designer (FFW-004) Azista BST Aerospace Plot No. 16, Sanand Land Industrial Estate Corporation, Sarkhej-Sanand Road, Ularia, Sanand, Ahmedabad, Gujarat, India - 382 210. Registered Office Sy.No 80-84, Melange Towers, 4th Floor, C Wing, Patrika Nagar, Madhapur, Hyderabad, Telangana, India - 500 081.

The selected candidate will be responsible for implementing high-speed high-volume data generation and handling requirements on FPGA-based hardware, including storage in and playback from SSDs/SSRs and high-speed serial (SERDES, going to several Gbps) / Parallel (LVDS exceeding a hundred MHz). The subsystems are for use in state-of-the-art spaceborne payloads for high-performance applications in indigenous private-sector satellites in India. The work typically may involve, but not necessarily be limited to, the following activities: Understanding hardware component/environment capabilities, requirements and limitations and evolving firmware architectures and coding for required performance goals. Be a team contributor, code for parts of a larger functionality and seamlessly integrate and test the integrated firmware Partake in the full development cycle and not just design or verification, and be responsible for subsystem level outcomes in an integrated system Prepare documents necessary at different stages and be able to interact with QA/QC guidelines and facilitate assurance of code compliance to a given standard As a general rule, Azista requires that all engineers take an enthusiastic part in whatever activity they are required to contribute to in order to make the missions and the company successful. The knowledge base required in the candidate will in general be a clear understanding of the fundamentals of Coding for FPGA environment, a significant experience profile of doing this. Excellent familiarity and skill in VHDL (or Verilog) Knowledge of the architectures of modern high-density FPGAs and SoC Devices from Xilinx (Now AMD) or Actel (Now Microchip) FPGAs and familiarity with the use of these Excellent familiarity with the development environments for these devices and the simulation and pre-burn performance validation tools Very good experience in actually porting developed code into the hardware platforms and testing the same for target performance characteristics, and the skill in spotting problems and be able to relate observations in tests back to necessary refinements in code Exposure to safe coding practices and high-reliability engineering Specific successful design experience with at least one of the following: Implementation of high-speed SERDES data links going to several Gbps and testing for the same Implementation of SSD interfaces and familiarity with modern SSD interface standards Implementation of gigabit ethernet solutions in FPGA environments and testing for the same The successful candidate is likely to have An electronics degree, masters preferred but not necessary A consistent career in FPGA-based firmware design and coding (6 to 10 years at least) with exposure to high-density Xilinx (Now AMD) or Actel (Now Microchip) FPGAs with many designs turned out successfully Good experience in debugging systems, including the ability to probe hardware and make sense of the time domain/frequency domain observations A good knowledge of how to estimate rough-order-of-magnitude power consumption figures even before a full design is evolved Note: Interviews are likely to be multi-level and very detailed. Please who do not check most of the points above may not be suitable at all. A consistent career in FPGA-based firmware design and coding (6 to 10 years at least) with exposure to high-density Xilinx (Now AMD) or Actel (Now Microchip) FPGAs with many designs turned out successfully Azista BST Aerospace Plot No. 16, Sanand Land Industrial Estate Corporation, Sarkhej-Sanand Road, Ularia, Sanand, Ahmedabad, Gujarat, India - 382 210. Registered Office Sy.No 80-84, Melange Towers, 4th Floor, C Wing, Patrika Nagar, Madhapur, Hyderabad, Telangana, India - 500 081.

FPGA design engineer will take part in the design domains of signal processing and data processing, image processing, other high-speed and control applications, implementing these functions on high-density state of the art FPGAs. Work may include specifying, architecture/microarchitecture definition and hands-on implementation work for every aspect of FPGA design, working closely with the system, software, and FPGA design and verification, guide and mentor juniors in the areas and Delivery of expert level technical support in the resolution of FPGA application issues at programming level. In addition to the FPGA implementation, the engineers are expected to understand subsystem/algorithm level behaviour of such designs and be able infer the necessary hardware design/resources necessary for a given subsystem level specification. Work may involve HDL level coding/verification/testing and/or System C coding levels and taking ownership of all aspects of the design verification of the FPGA chips and/or its functional blocks. Examples of possible micro streams of work: CCD/CMOS Image array readout at high speeds Formatting such data and serial or parallel transmission of the same to other subsystems Implementation of complex image or signal processing algorithms Implementation of i/o rich control functions to interface a large number of subsystems to central controllers. Working closely with microcontroller programmers, instantiation of controllers with sequential code inside FPGAs etc mapping algorithms and standards (PCIe, NVMe, SATA,USB, Ethernet, TCP/IP, TCP/IP off load engine (TOE), SERDES, LVDS, and Memory Controllers DDR2/DDR3 ) to hardware and architecture/system design trade-offs standard bus protocols, including I2C, SPI, USB, PCIe. Candidates should preferably have good quantitative aptitude and understand analy Content coding like Verilog/VHDL, or System C or equivalent, exposure to complex/high density FPGAs and FPGA-SoCs Familiarity with Matlab and Simulink Vitis Unified Software Platform - Xilinx or similar Bachelors in Electronics or equivalent stream and a minimum of 10 years experience or Masters Degree in a related specialization with a minimum of 8 years experience in Electronics Design/Embedded Electronics, out of which the most recent 6 years must have been in state of the art high density FPGA environments. FPGA Design Engineer Azista BST Aerospace Plot No. 16, Sanand Land Industrial Estate Corporation, Sarkhej-Sanand Road, Ularia, Sanand, Ahmedabad, Gujarat, India - 382 210. Registered Office Sy.No 80-84, Melange Towers, 4th Floor, C Wing, Patrika Nagar, Madhapur, Hyderabad, Telangana, India - 500 081.

The selected candidate will be responsible for evolving hardware designs for specialized electronic subsystems (going to hundreds of MHz operational frequency, tens of Gbps data throughput and involving devices like FPGAs with thousand pins or more) based on subsystem functional requirements available from system designers. The work typically may involve, but not necessarily be limited to, the following activities: Understanding subsystem requirements available from system designers and identifying a core electronic hardware architecture to fulfil the same Identify a suitable critical BoM commensurate with the functional requirements and project schedules Prepare block-diagram level design and present for review Initiate procurement activity for the components Prepare (or help preparation of, as the case may be) schematics for the designs and design analysis documents for review Guide the design of PCBs (likely to be multilayer high-speed boards with FPGAs of 1000 pins or more) Oversee outsourced component mounting in accordance with quality requirements Carry on board bring up tests Interact with software designers to prepare appropriate test cases and exercise the external ICD and on-board performance parameters Test the design for integrity over temperature, vibration and vacuum tolerance and other environmental validation requirements (may involve EMI/EMC also) Hand over the qualified hardware to software designers to take the development forward. Present the designs to various reviews during the developmental and project phases and incorporate the respective comments As a general rule, Azista requires that all engineers take an enthusiastic part in whatever activity they are required to contribute to in order to make the missions and the company successful. The knowledge base required in the candidate will in general be a clear understanding of the fundamentals of Circuit theory and electronics in general, the behaviour of different electronic components Good skills in reading and understanding data sheets, interpreting data sheet information qualitatively and quantitatively and know how to translate them into schematic-level topographies Knowledge of how to build schematics including high-density devices like FPGAs with more than a thousand pins The nuances of high-speed high-density designs and a good knowledge of PCB design fundamentals to guide the PCB designers properly for ensuring intended performance. The successful candidate is likely to have An electronics degree, masters preferred but not necessary A consistent career in hardware design of (6 to 10 years at least) with exposure to high-density Xilinx (Now AMD) or Actel (Now Microchip) FPGAs Exposure to high-speed and/or RF design (Only RF design is NOT suitable) A desirable experience in high-speed SERDES-based designs with modern FPGAs Exposure to high-speed data handling and memory interfacing like DDR3/4 A knowledge of how to do peripheral design around modern high-speed FPGAs like decoupling needs, power quality and POL conditioning including meeting sequencing needs A good knowledge of how to estimate rough-order-of-magnitude power consumption figures even before a full design is evolved Note: Interviews are likely to be multi-level and very detailed. Please who do not check most of the points above may not be suitable at all. A consistent career in hardware design of (6 to 10 years at least) with exposure to high-density Xilinx (Now AMD) or Actel (Now Microchip) FPGAs Azista BST Aerospace Plot No. 16, Sanand Land Industrial Estate Corporation, Sarkhej-Sanand Road, Ularia, Sanand, Ahmedabad, Gujarat, India - 382 210. Registered Office Sy.No 80-84, Melange Towers, 4th Floor, C Wing, Patrika Nagar, Madhapur, Hyderabad, Telangana, India - 500 081.

Senior Principal Software Engineer The Software Engineering team delivers next-generation software application enhancements and new products for a changing world. Working at the cutting edge, we design and develop software for platforms, peripherals, applications and diagnostics all with the most advanced technologies, tools, software engineering methodologies and the collaboration of internal and external partners. Join us to do the best work of your career and make a profound social impact as a Senior Principal Software Engineer on our 5G RAN FPGA Team in Bangalore What you ll achieve As a Senior Software Principal Engineer, you will be responsible for developing sophisticated systems and software basis the customer s business goals, needs and general business environment creating software solutions. You will: Design and lead the effort on automation, CI/CD processes and tools to make our services simpler and more robust Mentor team members in design collaboration, code reviews, development tools and processes Take part in the full software development life cycle including development, test, continuous delivery and support Be an active member of an agile team, collaboratively realizing features through development, test and delivery Take the first step towards your dream career Every Dell Technologies team member brings something unique to the table. Here s what we are looking for with this role: Essential Requirements Expert in designing, implementing, and testing new blocks for FPGA Radio platforms Expertise in NR/LTE/eCPRI/CPRI/PTP protocol analysis and implementation with signal processing knowledge and background 5G Radio development background Expert in closing timing on an Intel/Xilinx FPGA. Expert in integration of IP/RTL into Intel/Xilinx FPGA. Strong problem-solving and analytical skills.Agility to adapt to technologies and processes quickly Desirable Requirements 13-16 years of relevant experience or equivalent combination of education and work experience Experience with FPGA design tools like Quartus. Experience in MATLAB and Simulink modelling for 5G flow Application closing date: 20 July 2025

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Description / Summary Join our elite North America hardware application engineering team, and work closely with the best AEs, PEs and R&D in EDA industry. Join a top class company that has been listed in Fortune magazine and Great Place to Work as one of the World's Best Workplaces™ for the eleven years in a row! You will report directly into the North America Verification Field Applications Engineering (FAE) Team, and be co-located in India alongside our R&D teams. You will be a leading product expert on advanced FPGA based prototyping focusing on Cadence’s Protium X3 system . Your focus will be to work on key campaigns in North America, driving differentiated HW emulation solutions at our industry leading semiconductor and system companies and you will form a key bridge between our customers, North America AEs and R&D teams. Key Responsibilities Assume technical leadership for Protium compiler flow and become the go-to expert for the rest of the North America field AE team . Provide in-depth technical assistance in collaboration with R&D to help support advanced Protium based flows to secure design wins . Champion the customer needs and work closely with R&D in India to develop competitive and creative technical solutions. Strong experience in FPGA based emulation or prototyping. Experience in portioning for Xilinx FPGA’s and analyze bottlenecks to performance. Knowledge of interface bring up on FPGA platforms like PCIe and DDR Experience with SystemVerilog, VHDL, Verilog, C/C++/SystemC Strong verbal and written communication skills, with the ability to effectively bridge communication channels between external customers, NA FAE team and internal R&D teams. Strong teamwork skills 12+ years industry experience We’re doing work that matters. Help us solve what others can’t.

Role & responsibilities FPGA, RTL, DO-254,VHDL, VERILOG, XILINX, LIBERO, AVIONICSJ Preferred candidate profile

Position Title : Assistant Professor Department : Electronics and Communication Engineering (ECE) Institution : MNR University Location : Sangareddy Employment Type : Full-Time Compensation : As per institutional norms and experience level Role Summary We are seeking a qualified and motivated Assistant Professor in the Department of Electronics and Communication Engineering , with a strong academic background and industry-aligned research experience in VLSI Design, Embedded Systems, Advanced Communication Systems , and Internet of Things (IoT) . The selected candidate will contribute to teaching, research, and departmental development. Key Responsibilities Teaching & Mentoring Deliver engaging lectures and lab sessions for undergraduate and postgraduate ECE courses. Teach specialized subjects in VLSI Design, Embedded Systems, Advanced Communication Techniques, and IoT. Guide students in major/minor projects, thesis work, and technical competitions. Design modern teaching content using digital platforms and tools. Research & Publications Undertake high-quality research in relevant domains and publish in peer-reviewed journals and reputed conferences. Collaborate on interdisciplinary projects and apply for funded research grants. Supervise student research and contribute to building a research-driven environment. Academic Contribution Participate in curriculum development and syllabus revision aligned with NEP and industry trends. Support the department in accreditation processes (NAAC/NBA) and academic audits. Organize and contribute to FDPs, workshops, technical fests, and seminars. Institutional Engagement Take part in departmental activities, academic committees, and institutional outreach programs. Engage in consultancy, MoUs, and industry-academia collaborations, wherever applicable. Eligibility Criteria Educational Qualification: Ph.D. awarded in Electronics and Communication Engineering or closely related area, with specialization in VLSI, Embedded Systems, IoT, or Communication Systems. B.Tech and M.Tech/M.E. in ECE or related field with First Class or equivalent. Experience: Minimum 2 to 7 years of post-Ph.D. academic/industry experience in a reputed institution or organization. Required Skills and Expertise In-depth knowledge in at least two or more of the following areas: VLSI Design & Verification Embedded System Design & Programming Advanced Communication Systems (5G, Wireless, OFDM, MIMO, etc.) Internet of Things (IoT) and Cyber-Physical Systems Proficiency in relevant tools and platforms (e.g., Xilinx, Cadence, MATLAB, Keil, NS3, Arduino, Raspberry Pi ). Excellent classroom management and communication skills. Familiarity with Outcome-Based Education (OBE) and Bloom’s Taxonomy . Capacity to initiate research projects and mentor student-led innovations.

Digantara is a leading Space Surveillance and Intelligence company focused on ensuring orbital safety and sustainability. With expertise in space-based detection, tracking, identification, and monitoring, Digantara provides comprehensive domain awareness across regimes, allowing end users to have actionable intelligence on a single platform. At the core of its infrastructure lies a sophisticated integration of hardware and software capabilities aligned with the key principles of situational awareness: perception(data collection), comprehension(data processing), and prediction (analytics). This holistic approach empowers Digantara to monitor all Resident Space Objects(RSOs) in orbit, fostering comprehensive domain awareness. Digantara seeks a highly skilled Senior Embedded Software Engineer to design and develop embedded software solutions tailored specifically for real-time image processing. You will leverage your expertise to enable the development of state-of-the-art embedded software with applications such as tracking objects from both space and the Us ? Be part of a collaborative and innovative environment where your ideas and skills make a real difference to the entire space realm. Push the boundaries with hands-on experience, greater responsibilities, and rapid career advancement. Competitive incentives, galvanizing workspace, blazing teampretty much everything you have heard about a : Design, develop, and implement embedded software for real-time image processing for satellite payload applications. Translate and optimize image processing algorithms to FPGA/SoC platforms to achieve low latency and high throughput. Collaborate with system-level designers and hardware designers, generate software functional requirements and architecture, and ensure seamless integration of software and hardware. Collaborate effectively with cross-functional teams to conceptualize, design, and implement optimal embedded software solutions for image processing. Define and implement interface and communication protocols for data handling between the satellite payload and bus systems. Develop clean, well-structured, maintainable code and execute comprehensive testing according to space industry standards (e.g., the ECSS software engineering standard). Implement rigorous software quality assurance practices, including static analysis, code coverage analysis, and other verification techniques. Develop efficient embedded software for high-performance embedded systems with the ARM Cortex processor architecture. Leverage AMD-Xilinx/Microchip EDA tools (e.g., Vivado/Vitis IDE, Libero SoC design suite) to develop efficient embedded software solutions. Troubleshoot and resolve embedded software defects and hardware interface Qualifications : B.Tech 5+ years of experience in Embedded software design and development, with a strong focus on image processing and experience in handling communication protocols. Strong proficiency in bare-metal and RTOS programming for embedded systems, with expertise in real-time scheduling, interrupt handling, and device drivers. Proven ability to optimize embedded software implementation, including code optimization, memory management, and power efficiency techniques. Proficiency in Embedded C and C/C++ programming languages. Strong understanding of data communication protocols such as I2C, UART, SPI, CAN, Gigabit Ethernet, LVDS, RS422, etc. Working knowledge of software configuration management tools and defect tracking Skills : Prior experience in embedded software implementation in the areas of satellite imaging payload or ground-based imaging systems is highly preferred. Working knowledge of FPGA/SoC-based embedded systems designed for image processing applications is highly valued. Experience in hardware-related programming of FPGA interfaces and high-level synthesis. Knowledge of implementing fault-tolerant embedded systems for satellite applications. Familiarity with digital image processing and implementation. Experience in Python programming language and knowledge of Verilog/VHDL. Experience with camera interfaces such as USB3, CoaXPress, CameraLink, PCIe, Gigabit ethernet, etc. General Requirements Ability to work in a mission-focused, operational environment. Ability to think critically and make independent decisions. Interpersonal skills to enable working in a diverse and dynamic team. Maintain a regular and predictable work schedule. Writing and delivering technical documents and briefings. Verbal and written communication skills as well as organizational skills. (ref:hirist.tech)

Minimum qualifications:. Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.. 15 years of experience in ASIC RTL design.. Experience with RTL design using Verilog/System Verilog and microarchitecture.. Experience with ARM-based SoCs, interconnects and ASIC methodology.. Preferred qualifications:. Master’s degree in Electrical Engineering or Computer Engineering.. Experience driving multi-generational roadmap for IP development.. Experience leading interconnect IP design team for low power SoCs.. About The Job. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.. Responsibilities. Lead a team of people to deliver fabric interconnect design.. Develop and refine RTL design to aim power, performance, area, and timing goals.. Define details such as interface protocol, block diagram, data flow, pipelines, etc.. Oversee RTL development, debug functional/performance simulations.. Communicate and work with multi-disciplined and multi-site teams.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less

Role: FPGA Engineer Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Proven experience in FPGA design and development, with a focus on RTL coding using Verilog or VHDL. Deep understanding of computer architecture, digital design principles, and hardware/software co-design concepts. Experience with high-frequency trading systems and ultra-low latency design techniques is highly desirable. Proficiency in FPGA development tools and workflows, such as Xilinx Vivado or Intel Quartus. Strong analytical and problem-solving skills, with the ability to optimize designs for performance, power, and resource utilization. Excellent communication and collaboration skills, with the ability to work effectively in a fast-paced, team-oriented environment.

Position: Lead RTL Design Engineer (ASIC/FPGA) Location: Bangalore Experience: 7+ years Senior / Lead Level Role Overview Were seeking a proactive Lead RTL Engineer to define micro-architectures, implement robust RTL, guide integration, and collaborate across ASIC and FPGA domains. You will architect complex subsystems and mentor a high-performing team. Key Responsibilities Micro-architecture & Specifications: Create block-level design docs & detailed RTL micro-architecture for highcomplexity IP/subsystems. RTL Coding & Review: Develop clean, synthesizable RTL in Verilog/SystemVerilog/VHDL. Ensure code quality via lint/CDCC/static timing checks. Integration & IP Subsystems: Integrate with SoC/FPGA subsystems—protocols like AMBA/AXI, interconnects, memory, serial interfaces. Synthesis & Timing Closure: Lead flows using Design Compiler, Primetime, STA tools to meet timing and area goals. Verification & Debug: Coordinate with verification leads, support testbench development, and debug RTL—functional, wavebased, simulation. Leadership & Mentorship: Mentor engineers, lead reviews, steer integration, and liaise across RTL, verification, physical design, and architecture teams. Toolchain & Scripting: Script for automation (Tcl, Python, Perl, Shell); manage version control (e.g. Perforce, Git) . Innovation & Best Practices: Drive RTL design best practices, stay current with EDA tools, lowpower (UPF), CDC, linting, and continuous improvement. Required Qualifications Bachelor’s/Master’s in EE/CE or similar. 7+ years in RTL for ASIC/FPGA, +3 years in a leadership role. Expert in Verilog/SystemVerilog/VHDL, microarchitecture, FSMs, datapaths, CDC. Experienced with SoC/IP integration—AXI, AHB, APB, PCIe, USB, Ethernet, DDR, etc. Proficient with synthesis, STA, CDC, lint tools, DFT flows. Solid scripting with Tcl/Python/Perl/Shell and version control systems. Strong communication, documentation, team leadership, and cross-team collaboration skills. Preferred Skills FPGA prototyping and hardware bring-up expertise. Low-power methodologies (UPF, power gating). ASIC methodology experience (synthesis, timing, DFT, PPA closure). Familiarity with UVM verification, formal methods. Integration experience with high-speed or accelerator IP (NoC, memory controllers, etc.). What You’ll Get High-impact leadership in advanced RTL design for ASIC/FPGA cutting-edge chips. Opportunity to mentor and build a top-tier RTL team. Collaborative culture working with architecture, verification, PD, and system teams. Learning, ownership, and visibility across end-to-end chip delivery.