95 X86 Jobs

Project description Performance Analyst in the compiler team is responsible for analyzing C/C++/Fortran benchmarks to identify the new compiler optimization opportunities as well as compiler shortcoming in terms of performance. The analysis will involve using various tools to identify the bottlenecks, root cause analysis and quantifying the analysis to confirm the gains obtained. The Performance Analyst will use this report to convince and drive the improvements in the compiler. The Performance Analysis Engineer will be responsible for conducting a detailed performance analysis on SPEC CPU and other key benchmarks. The role involves using compilers such as AOCC, and other key x86 compilers to evaluate performance on client and competitive platforms. The engineer will collaborate with cross-functional teams to drive performance improvements and ensure optimal product performance. Responsibilities Conduct performance analysis and optimization of SPEC CPU and other benchmarks on x86 architecture using AOCC and other competitive x86 compilers. Utilize profiling and debugging tools to identify performance bottlenecks and provide actionable insights. Collaborate with software development teams to implement performance improvements. Analyze instruction set architecture (ISA) to optimize code execution and efficiency. Engage in root cause analysis for performance-related issues and drive them to resolution. Develop and maintain scripts and tools for automated performance testing and data collection. Prepare detailed reports and presentations on performance findings and recommendations for stakeholders. Stay updated with the latest developments in compiler technologies and performance analysis methodologies. Communicate key findings and status updates to stakeholders and cross-functional teams. Skills Must have Minimum of 3 years of experience in performance analysis or a related field. Strong expertise in x86 architecture and instruction set architecture (ISA). Strong understanding of hardware and software system architecture and their implications on performance. Excellent programming/debugging skills at the Assembly level. Proficiency in using compilers such as AOCC, LLVM, GCC, and OneAPI. Experience with performance benchmarking tools and methodologies. Solid practical C/C++/Fortran experience Familiarity with both Windows and Linux operating systems for performance analysis. Ability to work in a fast-paced, deadline-driven environment. Excellent analytical skills and attention to detail. Strong communication skills, both written and verbal. Excellent analytical and problem-solving skills. Nice to have Strong communication skills and the ability to work collaboratively in a team environment. Other Languages EnglishB2 Upper Intermediate Seniority Regular

you will: Develop and integrate products deployed by leading service providers worldwide. Collaborate with a vibrant, BU-wide technical community to exchange ideas and innovate on next-generation technology. Explore opportunities for personal growth while mentoring colleagues and working on cutting-edge technologies. As a key member of this team, you will: Work alongside seasoned engineers to architect, design, and develop some of routers and solutions for the world's largest service provider, web centers, and enterprises. Contribute to the evolution of these systems to support exciting new customer business paradigms. Interact and collaborate with some of the finest talent in the industry, making work both fun and challenging. Engage with other groups such as Product Management, Marketing, Sales, Customer Support, and Advanced Services. Who You Are: You possess: In-depth knowledge of C and a solid understanding of Python. Extensive experience in a Unix/Linux-based development environment. Excellent coding, automation, and debugging skills. Strong teamwork and communication skills. Familiarity with hardware architectures such as PCI, PCIe, DMA, I2C, SPI , NPUs/DPUs and processors like x86, AMD, and ARM . Experience with board bringup is a plus. Experience with emerging technologies such as AI/ML and cloud computing is a plus. Experience and Qualifications: Experience: 9 to 12 years in embedded firmware development. Education: BE/B.Tech/ME/M.Tech/MS in CS/EE/IT/ECE, MCA, or similar education. Proven ability to derive design and code based on technical standards and write comprehensive, focused design documents. Experience in developing software/firmware for networking equipment. Excellent knowledge of software architecture and system design.

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of load store unit verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Lead the unit level pre-silicon functional & performance verification the Load Store Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for LSU, including the Load and Store pipelines, D-Cache, Address translation, out of order execution of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of load store unit verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Our Employees Are valued and empowered, collaborative and team oriented, innovative in their approach and passionate about their work. They are reliable, trustworthy and open with a high level of integrity. They value diversity, are inclusive and are committed to a global mindset. About the Product Using high-performance DNS services, Global Traffic Manager (GTM) scales and secures your DNS infrastructure during high query volumes and DDoS attacks. It delivers a complete, real-time DNSSEC solution that protects against hijacking attacks. GTM improves the performance and availability of your applications by intelligently directing users to the closest or best-performing physical, virtual, or cloud environment. In addition, enables mitigation of complex threats from malware and viruses by blocking access to malicious IP domains. Position Summary Our team is at the cutting-edge of DNS technology. We are focused on providing customers with solutions to improve access to applications by securing and accelerating Domain Name resolution. Collaborations with F5 s Firewall and Hardware teams produce unique opportunities for cross-team development projects.This position is for a Software Engineer III with experience designing and developing application data management software. The engineer will collaborate with software architects and other technical leads to design software and interfaces for our next generation features.We are looking for talented software engineers with a track record of accomplishment in the design, implementation and maintenance of major software features. Appropriate candidates should also have a knack for delving into complex customer configurations and delivering rapid fixes for critical issues. Responsibilities Develop new feature and software solutions for the F5 DNS products in areas such as: DNSSEC and similar security-related functionality. Ultra High Performance DNS server and resolver technology. Next generation geolocation technology. Document software designs via functional specifications and other design documents. Diagnose and resolve customer-facing issues, ranging from point fixes to complete feature re-implementation Evaluate performance data, tune and re-evaluate designs and implementations of current source code. Research, investigate, and define new areas of technology to enhance existing F5 DNS products. Document bug fixes and known issues for customer access Work collaboratively with other development team within F5 to create solutions for complex issues Qualifications 3+ year of professional experience in multi-platform network software development, in a commercial production environment. Bachelor degree in computer/engineering related field or equivalent work experience Proven programming skills/abilities in both C and C++ Development experience in areas such as sockets, multithreading, and data structure optimization. Familiarity with TCP/IP networking a strong plus. Experienced with at least one scripting language such as Python, Perl, Understanding of regexes Background in Unix based operating systems specifically, x86/Linux Strong problem-solving and analytical skills Proven ability to deliver products with highest quality and on time Strong written and verbal communications skills Ability to collect and document user specifications Ability to interact and communicate effectively with users of our products Physical Demands and Work Environment Daily computer use in an office environment. Occasional need to install computer equipment in racks and replace existing equipment. Equipment includes servers, routers, power supplies, and network appliances. Benefits: We provide competitive salaries, a world class benefits package, including 100% of the premium for employee medical, dental and vision insurance, highly subsidized premiums for dependent coverage, 401K match, employees stock purchase plan, 18 days paid time off within the 1st year and 9 paid holidays, life insurance, short & long term disability insurance, tuition reimbursement, and much more. The is intended to be a general representation of the responsibilities and requirements of the job. However, the description may not be all-inclusive, and responsibilities and requirements are subject to change. Please note that F5 only contacts candidates through F5 email address (ending with @f5.com) or auto email notification from Workday (ending with f5.com or @myworkday.com ) . Equal Employment Opportunity It is the policy of F5 to provide equal employment opportunities to all employees and employment applicants without regard to unlawful considerations of race, religion, color, national origin, sex, sexual orientation, gender identity or expression, age, sensory, physical, or mental disability, marital status, veteran or military status, genetic information, or any other classification protected by applicable local, state, or federal laws. This policy applies to all aspects of employment, including, but not limited to, hiring, job assignment, compensation, promotion, benefits, training, discipline, and termination. F5 offers a variety of reasonable accommodations for candidates . Requesting an accommodation is completely voluntary. F5 will assess the need for accommodations in the application process separately from those that may be needed to perform the job. Request by contacting accommodations@f5.com .

Lead the architecture, design and development of Processor Core Front end of pipeline units for high-performance IBM Systems. - Architect and design I-Cache, Instruction Fetch, Branch Prediction and Decode units of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) - Hands on experience of different Branch Prediction techniques - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Knowledge of at least one object oriented or functional programming language and scripting language. - Nice to haves - Knowledge of instruction decode and handling pipeline hazards - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Master's Degree/PhD

Lead the unit level pre-silicon functional & performance verification the Load Store Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for LSU, including the Load and Store pipelines, D-Cache, Address translation, out of order execution of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of load store unit verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

- Lead the architecture, design and development of Power Management for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Estimate the overall effort to develop the feature - Estimate the silicon area required for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Server SoC power management features. * Experience with hardware to model correlation * At least 1 generation of silicon bring up experience * In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) * Proficiency of RTL design with Verilog or VHDL * Knowledge of at least one object oriented or functional programming language and scripting language. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Working mode : Regular Notice Period : Immediate - 15 Days Mandatory Skills : - 3-7 years of experience in the x86 BIOS/UEFI development - Experience with x86 CPU/APU architectures and associated compilation tools - Expert in C language - Familiar with at least one BIOS code base (AMI, Insyde, or Phoenix BIOS) - Experience of working on UEFI bootloader or UEFI applications mainly involved in UEFI based storage protocols AHCI, SATA, NVMe. - Will be good if have any experience in Android UEFI based Bootloader for x86. - Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required. - Good understanding of UEFI framework concepts and Storage protocols. Additional Skillset : - Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. - Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. - Good understanding of industry standard protocols like SATA, NVMe, AHCI, PCIe, SPI, eSPI etc. - Good understanding of specifications like ACPI, SMM. - Good understanding of x86-64 architecture from BIOS developer's perspective. - Good understanding of UEFI BIOS Boot flow. Academic credentials: - Bachelor's degree in computer science engineering from reputed college - Master's degree from reputed university is a big plus .

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of load store unit verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Greetings from HCL Technologies...! Experience- 5 to 12 Years Location- Bangalore/Chennai Job Description: Work on key components of functional validation of complex ASIC SOC blocks on Emulation / HAPS / Post silicon platforms Experienced in one or more of following protocols Ethernet 802.3 protocols/IP, L2/L3, PCIE, DDR/HBM, ARM/RISC-V based CPU SS, USB, Audio & DSP, AI accelerators etc. Perform Pre/Post-Silicon test content and test plan development. Regress test plan execution and infrastructure development for functional validation of complex design. Creating stress and performance scenarios to meet test plan goals. Debug failures Experienced with Source and Version Control management (GIT/Perforce/CVS etc.) Innovate to improve validation efficiency through methodologies and tools Skills: Hands on experience with C/C++ and Python is must to have. Familiarity with boards, components, memories, industry standard interfaces like Ethernet, PCIE, DDR, HBM, USB, JTAG , I2C and UART protocols . Creativity, verbal and written communication skills, analytical and problem-solving ability.

Greetings from HCL Technologies..! Experience- 5 to 10 Years Location- Bangalore Job Description: Core UEFI BIOS code Firmware development. Strong knowledge on UEFI BIOS Framework and EDKII development kit Hands on in "C" / embedded SW/FW development Standard programming practice. and Debug Should have understanding on system level programming and debugging x86 architecture knowledge Should have good command on oral and email communications. Good to have understanding and worked on PC BIOS features development

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Job Summary If you are a Embedded software engineering professional, Emerson has an exciting role for you! We are looking for a Embedded software engineer to work with our controls and software team. This role will work independently and as a part of a team and will be involved in development of real-time embedded software user stories and implement requirements with a focus on quality and performance. You must have a passion for learning, and the ability to apply that learning in a practical manner to your high-quality work In This Role, Your Responsibilities Will Be: As an Embedded Software Engineer, you will use your software skills to develop new features and solve customer problems in our control system products. Work in small, self-motivated teams collaborating with global Scrum teams. Be involved in all phases of software development from product definition to production release. Use Agile software development practices to build and test our products using Continuous Integration. Break down problems and estimate time for development tasks. Work with cross functional teams (i. e. Software, Hardware, System Test and Product Management) to accomplish your assignments. Develop deep domain expertise while working on various assignments in control system platforms. Drive world-class quality in the development and support of products. WHO YOU ARE You can take quick and decisive actions in constantly evolving, unexpected situations. Showing a tremendous amount of initiative in tough situations; is outstanding at spotting and seizing opportunities. Have a clear sense of ownership in accomplishing objectives despite obstacles and setbacks. Open to work collaboratively with others across the organization to achieve shared objectives. Like to encourage the expression of diverse ideas and opinions. For This Role, You Will Need: Bachelor s or master s degree in Computer science/Electronics and Communication/Electrical Engineering. 3 to 6 years of Embedded software development experience in with Intel x86/ ARM architectures-based microprocessors/controllers. Strong expertise and experience in C/C++ Programming languages Good Knowledge in RTOS concepts. Good understanding of TCP/IP, UDP and Serial based protocols like Modbus, Profinet, Profibus. . etc. Ability to read hardware schematics and use of debugging instruments like oscilloscope, logic analyzers. Experience with standard JTAG based debuggers for debugging the system. Experience with Agile development process. Good understanding of Continuous Integration and deployment systems used in software development. Strong analytical and problem-solving skills Strong written and oral communication skills Preferred Qualifications that Set You Apart: Experience with Programmable Logic Controllers Having firmware development experience with Xilinxs Ultrascale SOC is an added advantage Experience in scripting languages like Python Our Culture Commitment to You . .

System Programming with strong fundamentals in C Programming Experience in the area of Intel X86 processor-based system architectures, processor and chipsets, Memory management, Error management etc. Experience in EDKIi, Open-Source BIOS development and Initialization functionality for enterprise servers. In-depth understanding of Industry standards, such as, BMC, CPU (Intel X86), Intel PCH, MRC, PCle. HW debugging experience - ITP, Lauterbach or similar HW Debugging tools.

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of verification principles and coverage. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 6 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg.I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages.

We re looking for DevOps Engineer to: propose and implement systems enhancements improve security posture of the development tools and applications built using the tools monitor usage and performance, and troubleshoot server and software issues analyze complexity and feasibility of new or changed requirements within specified architecture, define platform requirement sizing and controlling components plan, evaluate, migrate, develop, implement, configure, test and roll out systems (hardware or software, networks, controls) analyze outages and defective states, initiating and monitoring measures to remedy them install and administer Continuous Integration and Continuous Deployment tools Youll be working in the Core Platform Engineering team. Its part of Group CTO which is part of the global Technology Services division. You ll be focusing on DevOps tools engineering, Azure infrastructure. The team is truly agile and distribute across multiple locations, as a result you will gain valuable experience working with world-class IT and Banking expertise (including Europe, US and APAC). Diversity helps us grow, together. That s why we are committed to fostering and advancing diversity, equity, and inclusion. It strengthens our business and brings value to our clients ideally 7 years of experience and good knowledge of RedHat Linux and Solaris x86 Unix environments with scripting skills GitLab / GitHub / Azure Kubernetes Service / TeamCity / Jenkins / Nexus Repo administrator with installation and configuration experience working experience in configuring project build automation using Maven, Gradle, etc. strong background regarding Continuous Integration build chain and the tools and development processes strong knowledge and hands on experience on Kubernetes good understanding of Networking and storage good scripting knowledge of Unix shell and windows PowerShell strong knowledge of helm strong analytic and problem solving skills

The job involves working on Cisco UCS AI Server platform development activities. This team develops Software and Firmware for Cisco UCS platforms. This includes development of Server BMC (a.k.a Cisco Coordinated Management Controller) Firmware, Software, tools and utilities. In this role, you will have the opportunity to lead the technical charter and provide technical vision for Baseboard Management Controller (BMC) activities. You will be part of the UCS AI Rack Server team, Bangalore, which is a key part of Ciscos Data Centre strategy. We are looking for hands-on Technical architects as applicants who strive in a fast paced start-up like environment. You will be part of a dedicated team and open communications, empowerment, innovation, collaboration and customer success are the foundations of the team. For further product info, please look at this link Responsibilities include: Senior Engineer in the AI Server BMC team Demonstrate a high degree of originality and innovation in design/development activities. Be a hands-on Engineer working across different architectures and environments. Work closely with Hardware Team for design, schematic review, hardware bring up and debug activities. Work closely with group of other architects/collaborators to define the complete design. Influence the design of interfaces between products to ensure interoperability. Design and develop software in a real-time Linux (or similar) OS environment for Cisco UCS server platforms. Design and develop system software to meet the specification of platform requirements. Comprehend newer, complex datacentre customer requirements and translating to engineering features. Who You Are Required Experience and Skills: Excellent Data Centre/Cloud platform engineering Expertise Excellent hands-on experience in Firmware, Device Driver and Embedded/Real time systems development. Good knowledge of x86 and ARM architectures. Very Strong Expertise in C and other programming language(s) expertise is a plus. Very Strong proponent of Design thinking and abreast of new architecture/design/development methodologies Excellent verbal and written skills and professional presentation. Desired Experience and Skills Experience in Server/Storage chassis platform technologies Hands on experience in management controller firmware development (BMC) and IPMI/Redfish. Experience in HW tools like JTAG debuggers, I2C analyzers, Oscilloscopes and flash memory programmers. Experience in Industry standard protocols like PCIe, NVMe, CXL and other Interconnect/Server technologies Experience with GIT/Bitbucket 8-12 Years of experience BE/BTech/ME/MTech in Electronics/Computer Science preferred.

Ensure issues are solved on time with quality. Lead complex debug efforts for internal Silicon findings to identify root cause and resolution. Manage and track technical issues, risks and priorities. Manage customer and executive communications, including program status, risks and opportunities. Publish debug program indicators to identify major roadblocks and drive changes to improve debug throughput. Evaluate at the end of every program milestone if the open issues are gating to go to the next milestone. Drive improvements to the debug process based on the program learnings. Preferred Skills: 15+ years or more of experience in validation roles involving debugging OS, FW, Silicon, and HW issues. Understanding of PC industry standard busses and their software stack, such as PCIe, CXL. Strong knowledge of X86 architecture, SoC design, memory, RAS & power management Extensive knowledge of system architecture, technical debug, and validation strategy Good understanding and experience in platform/ system level debug, Operating System, Device Drivers and System BIOS interactions. Excellent communication and coordination skill1. Detailed oriented, highly organized, able to prioritize, and juggle multiple work streams to tight deadlines. Experience in Technical program management. A thorough understanding of datacenter industry technologies and their software stack.

Role & responsibilities Bachelor's/Masters Degree in Electronics/Computer Engineering. 6+ years of in-depth experience in x86 architecture and hardware design. System design experience is preferred. Experience in schematics design tool like concept HDL, and supporting physical/Layout design activity, hardware bring-up and validation will be required. Knowledge and design experience of DDR3/4, PCIe, SERDES Technologies, Ethernet along with High-speed PCB design and signal integrity will be advantage. Good experience in Board Bring-up, Hardware and System level debugging Good understanding of interfaces like DDR-2/3/4, PCIe, SerDes protocols Good experience on management interface like SPI, I2C Proven experience on preparation of Functional Specifications, Production Definition and taking ownership on Documentation Hands on with the usage of design tools from Mentor Graphics and Cadence Hands on with the usage of Digital Oscilloscope, Multimeters, test and measuring equipment

Excellent big picture and abstract thinking skills, with an open & innovative mindset Exposure to entire life cycle of Embedded software deve process. Analytical skills, excellent communication & team building skills. Programming skills in C/C++ Required Candidate profile Bachelors or master’s in engg Electrical / Electronics Engg or Computers or equivalent.10+ yrs of exp in the dev of embedded programming (C, C ++) as well as scripting (Python) with 5 yrs in lead role