95 X86 Jobs - Page 4

Experience in embedded Linux x86/arm Embedded tools complier, debugger, rtos etc Exp in openwrt/ wireless routers Ex0 in digital design and communication protocol rs232, 422, 485, eternity etc

Develop high-quality platform validation software tools using C++. Write clean, maintainable, and efficient code. Collaborate with cross-functional teams to define, design, and add new features. Debug and maintain existing codebase to ensure software stability and performance. Participate in code reviews and provide constructive feedback to peers. Troubleshoot and resolve software issues as they arise PREFERRED EXPERIENCE: Extensive experience with C++ programming and basic knowledge on scripting languages like Python and shell script. Experience with QT, STL, Boost and any front end back end development in C++, ReactJS / AngularJS is plus. Software applications design and development experience. Ability to do RD and come up with design proposals. Experience in the Semi-conductor domain with CPU or GPU SW development experience. Should have good understanding of x86/ARM architecture. Experience in Memory, PCIe and USB domain would be good. Should have good analytical and debug skills. Ability to adapt to new technologies and learn quickly Good understanding of operating system internals is preferred (windows / Linux). Familiarity with Git version control system. Excellent communication skills to be able to not only work as part of the team but also interact and engage with other engineers at remote design centers. Various necessary soft skills such as ability to work with minimal input directions, teamwork, initiative and positive attitude. ACADEMIC CREDENTIALS: Bachelors or master s degree in electronics or computer engineering .

Responsibilities IBM Cloud Position in Bangalore, India for a Hardware Server Qualification support Engineer involving Programming, Automation, Security, Compliance, Qualification, Regression, Test, Diagnosis, and Repair. This role is related to component and server qualification for the latest x86 server technology, GPU accelerator technology (for Artificial Intelligence and Machine Learning workloads), and networking technology used in high density systems to support an enterprise Cloud customer base. The basic building blocks of cloud servers (compute, storage, and network) which include CPUs, NIC cards, Memory DIMMs, Drives, and S/W must qualified for the IBM public cloud. This position is for a hardware developer responsible for qualifying hardware and firmware used on various components, cards, and boards which make up the latest servers used in IBM-Cloud Datacenters. The individual will work on a small team focused on developing and qualifying integrated hardware solutions to support IaaS (Information as a Service) on best of breed Cloud Architecture. The individual should be very detail oriented with excellent documentation and communication skills. Programming experience (Linux and Python) along with Hardware knowledge and familiarity with x86 computer servers, components, and GPU based systems is preferred. The candidate should also be familiar with server hardware subsystems including processor memory storage, I/O adapters, PCI busses and switches, and BMCs. Familiarity with FW/BIOS updates and settings and network booting is preferred and knowledge of JIRA, Redfish, and xCAT, and security vulnerabilities/compliance along with patching of systems out of compliance is a definite advantage. Candidate is responsible for Qualification of Servers and System Qualification and support of Field Deployment * Booting Servers to test for existence and functionality of all components * Qualification of Server level Secure Boot and Memory Boot * Confirming all Secure Measures and encryption measures are compliant * Testing proprietary Baseboard Memory Control / OpenBMC on all server configurations * Automation of tests using Redfish for new products and regression on existing products * Qualification of each new vendor version of BMC, BIOS, and firmware codeHardware upgrades and network connections * Hardware upgrades and network connection Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise Ability to program using Linux and Python Good understanding/familiarity of Python coding/Redfish/ OpenBMC Comfortable with Server level BMC, BIOS, and firmware Automation of BMC and BIOS firmware updates to the field Familiarity with server bring-up including firmware/bios updates, bios settings, network boosting, and basic networking is very beneficial Clear Documentation and Communication of Results Strong understanding of server hardware and networking design Preferred technical and professional experience Proficient at Qualification/Verification of server & component level Hardware & Firmware Functions, and Data Analysis Familiarity with server hardware design including processors, memory, storage drives, I/O adapters, BIOS, and BMC Good understanding of server hardware and components (CPUs, DIMMs, Drives, NIC Cards, etc.) Safety certified to work around high voltages (480VAC and 208VAC) Hands on working experience in an engineering lab environment. Familiar with typical datacenter power, cooling infrastructure, and datacenter energy efficiency

Responsibilities Lead the unit level pre-silicon functional & performance verification the Load Store Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for LSU, includingthe Load and Store pipelines, D-Cache, Address translation, out of orderexecution of the high performance processor CPU. Develop verification test plan for both functional and performance verificationincluding the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensiveinsights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered andmilestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of load store unit verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools. ABOUT BUSINESS UNIT IBM Systems helps IT leaders think differently about their infrastructure. IBM servers and storage are no longer inanimate - they can understand, reason, and learn so our clients can innovate while avoiding IT issues. Our systems power the worlds most important industries and our clients are the architects of the future.Join us to help build our leading-edge technology portfoliodesigned for cognitive business and optimized for cloud computing. YOUR LIFE @ IBM In a world where technology never stands still, we understand that, dedication to our clients success, innovation that matters, and trust and personal responsibility in all our relationships, lives in what we do as IBMers as we strive to be the catalyst that makes the world work better. Being an IBMer means youll be able to learn and develop yourself and your career, youll be encouraged to be courageous and experiment everyday, all whilst having continuous trust and support in an environment where everyone can thrive whatever their personal or professional background. Our IBMers are growth minded, always staying curious, open to feedback and learning new information and skills to constantly transform themselves and our company. They are trusted to provide on-going feedback to help other IBMers grow, as well as collaborate with colleagues keeping in mind a team focused approach to include different perspectives to drive exceptional outcomes for our customers. The courage our IBMers have to make critical decisions everyday is essential to IBM becoming the catalyst for progress, always embracing challenges with resources they have to hand, a can-do attitude and always striving for an outcome focused approach within everything that they do. Are you ready to be an IBMer?

Responsibilities IBM Cloud Position in Bangalore, India for a Hardware Server Qualification support Engineer involving Programming, Automation, Security, Compliance, Qualification, Regression, Test, Diagnosis, and Repair. This role is related to component and server qualification for the latest x86 server technology, GPU accelerator technology (for Artificial Intelligence and Machine Learning workloads), and networking technology used in high density systems to support an enterprise Cloud customer base. The basic building blocks of cloud servers (compute, storage, and network) which include CPUs, NIC cards, Memory DIMMs, Drives, and S/W must qualified for the IBM public cloud. This position is for a hardware developer responsible for qualifying hardware and firmware used on various components, cards, and boards which make up the latest servers used in IBM-Cloud Datacenters. The individual will work on a small team focused on developing and qualifying integrated hardware solutions to support IaaS (Information as a Service) on best of breed Cloud Architecture. The individual should be very detail oriented with excellent documentation and communication skills. Programming experience (Linux and Python) along with Hardware knowledge and familiarity with x86 computer servers, components, and GPU based systems is preferred. The candidate should also be familiar with server hardware subsystems including processor memory storage, I/O adapters, PCI busses and switches, and BMCs. Familiarity with FW/BIOS updates and settings and network booting is preferred and knowledge of JIRA, Redfish, and xCAT, and security vulnerabilities/compliance along with patching of systems out of compliance is a definite advantage. Candidate is responsible for Qualification of Servers and System Qualification and support of Field Deployment * Booting Servers to test for existence and functionality of all components * Qualification of Server level Secure Boot and Memory Boot * Confirming all Secure Measures and encryption measures are compliant * Testing proprietary Baseboard Memory Control / OpenBMC on all server configurations * Automation of tests using Redfish for new products and regression on existing products * Qualification of each new vendor version of BMC, BIOS, and firmware codeHardware upgrades and network connections * Hardware upgrades and network connection Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise Ability to program using Linux and Python Good understanding/familiarity of Python coding/Redfish/OpenBMC Comfortable with Server level BMC, BIOS, and firmware Automation of BMC and BIOS firmware updates to the field Familiarity with server bring-up including firmware/bios updates, bios settings, network boosting, and basic networking is very beneficial Clear Documentation and Communication of Results Strong understanding of server hardware and networking design Preferred technical and professional experience Proficient at Qualification/Verification of server & component level Hardware & Firmware Functions, and Data Analysis Familiarity with server hardware design including processors, memory, storage drives, I/O adapters, BIOS, and BMC Good understanding of server hardware and components (CPUs, DIMMs, Drives, NIC Cards, etc.) Safety certified to work around high voltages (480VAC and 208VAC) Hands on working experience in an engineering lab environment. Familiar with typical datacenter power, cooling infrastructure, and datacenter energy efficiency

Responsibilities Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead, guide, mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress, potential challenges encountered and milestones achieved to stake holders and team members Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 15 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Responsibilities Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic units. Knowledge of test generation tools and working with ISA reference model.

Responsibilities Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools.

Responsibilities Lead the architecture, design and development of Processor Core Vector-Scalar Execution unit for high-performance IBM Systems. Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU Develop the features, present the proposed architecture in the High level design discussions Estimate the overall effort to develop the feature. Estimate silicon area and wire usage for the feature. Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in post silicon lab bring-up and validation of the hardware Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Execution unit of CPU Hands on experience of implementing Arithmetic/Crypto/SIMD functions Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Proficiency of RTL design with Verilog or VHDL Nice to haves Knowledge of instruction dispatch and load/store units Knowledge of verification principles and coverage High-level knowledge of Linux operating system Knowledge of one object oriented language and scripting language Understanding of Agile development processes Experience with DevOps design methodologies and tools Preferred technical and professional experience

Responsibilities Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead, guide, mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress, potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Knowledge of instruction dispatch and Arithmetic unit. Knowledge of test generation tools and working with ISA reference model. Experience with translating ISA specifications to testplan. Knowledge of verification principles and coverage. Understanding of Agile development processes. Experience with DevOps design methodologies and tools

Work Location : Bangalore, Belgrade, Penang, New York Work Expertise : 5 - 15 years Job Specs : - Expertise in the x86 BIOS / UEFI FSP / coreboot development - Expertise with x86 CPU/APU architectures and associated compilation tools - Expertise in C programming - Expertise with platform bring-up - Expertise with standard protocols like PCIe, SPI, eSPI, ACPI, SMM - Expertise with opensource coreboot project & mainboard related porting with GPIO, PCIe lanes, board fmd configs and board bring-up experience on customer platforms. - Expertise on working with Intel FSP package source code and understanding of coreboot & FSP boot flow - Expertise with different coreboot payloads like edk2, SeaBios, Tianocore etc - Ability to read platform Hardware and Processor specifications to understand the coreboot mainboard porting required - Good coreboot upstreaming exposure - Familiar with coreboot boot stages, upds, memory map, FSP, devicetree concept, payloads to OS bootloader handoff - Understanding of coreboot & FSP build tools and build processes - Good understanding of UEFI framework concepts to port UEFI code to FSP - Working knowledge of Git for code reviews, source code management, and BIOS releases to QA. - Ability to juggle tasks and respond to different teams for various requests for custom BIOS requirements. - Good understanding of x86-64 architecture from BIOS developer's perspective. - Good understanding of UEFI BIOS Boot flow. - Basic understanding of Linux Kernel like software development concepts (Kconfig).

Job TitleEngineer (DWDM Planning Tool Development) LocationBengaluru Work EmploymentFull time DepartmentWireless DomainSoftware Reporting toSenior Manager About Us: Tejas Networks is a global broadband, optical and wireless networking company, with a focus on technology, innovation and R&D. We design and manufacture high-performance wireline and wireless networking products for telecommunications service providers, internet service providers, utilities, defence and government entities in over 75 countries. Tejas has an extensive portfolio of leading-edge telecom products for building end-to-end telecom networks based on the latest technologies and global standards with IPR ownership. We are a part of the Tata Group, with Panatone Finvest Ltd. (a subsidiary of Tata Sons Pvt. Ltd.) being the majority shareholder. Tejas has a rich portfolio of patents and has shipped more than 900,000 systems across the globe with an uptime of 99.999%. Our product portfolio encompasses wireless technologies (4G/5G based on 3GPP and O-RAN standards), fiber broadband (GPON/XGS-PON), carrier-grade optical transmission (DWDM/OTN), packet switching and routing (Ethernet, PTN, IP/MPLS) and Direct-to-Mobile and Satellite-IoT communication platforms. Our unified network management suite simplifies network deployments and service implementation across all our products with advanced capabilities for predictive fault detection and resolution. As an R&D-driven company, we recognize that human intelligence is a core asset that drives the organization’s long-term success. Over 60% of our employees are in R&D, we are reshaping telecom networks, one innovation at a time. Why join Tejas: We are on a journey to connect the world with some of the most innovative products and solutions in the wireless and wireline optical networking domains. Would you like to be part of this journey and do something truly meaningful? Challenge yourself by working in Tejas’ fast-paced, autonomous learning environment and see your output and contributions become a part of live products worldwide. At Tejas, you will have the unique opportunity to work with cutting-edge technologies, alongside some of the industry’s brightest minds. From 5G to DWDM/ OTN, Switching and Routing, we work on technologies and solutions that create a connected society. Our solutions power over 500 networks across 75+ countries worldwide, and we’re constantly pushing boundaries to achieve more. If you thrive on taking ownership, have a passion for learning and enjoy challenging the status quo, we want to hear from you! Who we are: Our team submits contributions to the standards organization like IEEE, ITU-T, ITU-R, 3GPP RAN/SA, etc. and has generated more than 200 patents in various technology areas like TCP, IP/MPLS, MAC/Ethernet, SDH, DWDM, Routing, Scheduling, Optimization, Operation Research, 4G/LTE, 5G/NR, Protection Switching, etc. The team is expected to have a sound knowledge in the following theoriesstochastic processes and communication networking, RF circuit design and VLSI, digital signal processing, and operations research, and have sound programming skills for the purpose of prototyping in at-least one of the languagesC, C++, Python, VB, etc. Many next-generation prototypes developed by Technology domain team evolved to commercial grade products and have won many awards globally. What you work: As a technical member, you will contribute in regression and testing the state-of-the-art optical network planning system. Closely work with other teams and partners to carry out development, regression and user acceptance testing. Focus to continuously improve system performance with quality deliverables. Mandatory skills: Experience in DWDM planning tool development. Experience in Python, with knowledge of Django Framework. Familiarity with Django ORM (Object Relational Mapper). Familiar with various design and architectural patterns. Sound knowledge of Databases – MySQL, Postgres is a must. Hands on Linux operating system. Preference to candidates with exposure to ARM, Intel x86, etc. Architecture Desired skills: Linear Algebra, Probability, or any two Engineering Mathematics subjects, plus mandatory Computer networks. Additionally, if CS/ITData Structures and Algorithms, or any two core subjects. Additionally, if ECEStochastic Processes, Communication systems, or any two core subjects. Should be a team player. Should be curious to lear new things. Preferred Qualifications: E xperience: 1-3 years’ experience from Telecommunication, Opto-electronics or Optical Networking background. Education: Tech/BE/M.Tech/PhD (CSE/ECE/EEE/IS) or any other equivalent degree. Candidate should be good at coding skills in Python Diversity and Inclusion Statement : Tejas Networks is an equal opportunity employer. We celebrate diversity and are committed to creating all inclusive environment for all employees. We welcome applicants of all backgrounds regardless of race color, religion, gender, sexual orientation, age or veteran status. Our goal is to build a workforce that reflects the diverse communities we serve and to ensure every employee feels valued and respected.

Hiring for Linux Device Driver Developer. Mandatory skill set- C Linux device Driver Kernel module User space X86 multi core processor

Develop and optimize C/C++ applications for high-performance systems using OOP principles, multi-threading, and networking (TCP/UDP). Work on x86 and ARM-based systems, including microcontroller and processor-based designs (NXP, ARM architecture). Implement driver development for Ethernet, PCI, and communication protocols such as SPI, I2C, UART, Ethernet, RS422, and RS485. Configure and maintain bootloaders and ensure seamless interaction between kernel and user-space components. Develop software for ASIC prototyping in FPGAs using ARM core-based designs and AXI bus programming. Perform unit testing, integration testing, and software maintenance, ensuring adherence to quality standards. Collaborate with cross-functional teams to integrate software with hardware systems. Document technical processes and findings and present results to internal teams and stakeholders. Skills : - x86 ,ARM-based systems, microcontroller , processor-based designs, Ethernet, PCI, communication protocols, ASIC prototyping in FPGAs, ARM core-based designs and AXI bus, bootloaders, kernel/user-space interactions, and open-source tools

Essential Duties and Responsibilities: Responsible for defining, implementing, executing, and documenting embedded software for Baxter s peritoneal dialysis device portfolio. The activities will encompass all facets and phases of software development & test and life cycle management, meeting all regulatory and quality standards to realize complex, innovative, reliable systems that improve the quality of life for people around the world. Collaborate with other engineering and functional organizations to understand and define product use cases and convert these use cases into software requirements and design implementations. Own and lead all activities of software sub-system development and life-cycle management including sub-system development plans, SW requirements development, code development and optimization, unit and integration testing, SW risk and reliability analysis, root cause analysis. Transform software requirements into software architectures and verify that all software projects adhere to architecture standards. Lead concept selection efforts and design alternatives. Devise simulator solutions for the product portfolio. Drive research on emerging software architecture techniques and standards. Champion technical and industry trends related to software design and development Ensure all interface requirements are documented. Provide leadership to teams of engineers in multiple sites. Define the test automation strategy and implementation. Coordinate the software test activities with all other engineering disciplines, including external development partners. Qualifications Graduate or Post Graduate in Computer Science or related Engineering and 10 - 15 years of experience, including technical leadership. Prior experience in Renal device domain is a plus. A demonstrated track record in embedded software development, preferably medical devices or other highly regulated products such as military hardware. A proven track record of effectiveness in a fast paced environment. Experience in algorithms, code optimization, encryption, multiple language support C, C++, Assembly ARM processor development. Ability to work in a Linux development environment ARM / AVR processor development FPGA programming skills Intel embedded X86 development a plus Experience in embedded RTOS development Experience with USB, Ethernet, RS232 communications protocols Experience with sensor sampling Ability to develop boot loader code for microcontrollers Working level knowledge with standards such as IEC 62304, IEC 62366, IEC 60601, ISO 13485 and ISO14971 would be a plus.

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon RTL Design Engineer :- • Job Description o As a member of Design(RTL) team, you will be responsible for the microarchitecture and design of IPs/Controllers for SoC/SiP designs. o Perform architectural/design trade-offs for required product features, performance and system constraints. o Responsible for defining and documenting design specifications. o Develop and deliver a fully verified RTL to achieve the design targets and quality sign-off requirements. o Design and Implement logic functions that enable efficient test and debug. o Provide Debug support for design verification and post-silicon activities. • Skill and Experience Requirements: o Minimum 7 + years industry experience with Masters degree (preferred) or Bachelors degree in Electrical or Computer Engineering. o Hand-on experience with micro-architecture and RTL development (System Verilog) for x86/ARM CPU Processors or high-speed custom ASICs/Accelerators with focus on any one: Cache controller, IO interfaces (PCIe, CXL, Ethernet), UCIe, Memory controllers, Display, Video encoding/transcoding. o Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis and sign-off quality flows. o Self-starter with strong interpersonal and communication skills . o Excellent team player. .

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Staff Design Verification Engineer Job Description In this role you will be responsible Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role And Responsibilities Partner with Architects and RTL Design team to grasp high-level system requirements and specifications. Formulate comprehensive test and coverage plans to match the Architecture and micro-architecture. Define and implement a verification methodology that supports scalability and portability across various environments spanning including post-silicon. Develop the verification environment and reusable bus functional models, stimulus, checkers, assertions, trackers, and coverage metrics. Create verification plans and develop testbenches tailored to assigned IP/Subsystem or functional domain. Execute verification plans, including tasks such as design bring-up, setting up the DV environment, running regressions for feature validation, and debugging test failures. Support post-Si bring-up and debug activities. Track and communicate progress in the DV process by using key metrics like bug tracking and coverage reports. Requirements Bachelors or Masters degree in Electrical or Computer Engineering/Science Strong Architecture domain knowledge in x86/ARM CPU, or Memory, Coherency, Virtualization or Performance areas. Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 7yrs+ hands-on experience in IP/sub-system and/or SoC level verification Hands on experience and expertise with industry standard verification tools for simulation and debug (Questa/VCS, Visualizer) Experience using random stimulus along with functional coverage and assertion based verification methodologies a must. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation. Preferred Qualifications: Experience in development of UVM based verification environments from scratch. Hands on expertise and protocol knowledge in any of: APB/AXI/CHI, JTAG/I3C/SPI, , DDR5/LPDDR5/HBM, PCIE/CXL/UCIE/Ethernet compliance testing

At F5, we strive to bring a better digital world to life. Our teams empower organizations across the globe to create, secure, and run applications that enhance how we experience our evolving digital world. We are passionate about cybersecurity, from protecting consumers from fraud to enabling companies to focus on innovation. Everything we do centers around people. That means we obsess over how to make the lives of our customers, and their customers, better. And it means we prioritize a diverse F5 community where each individual can thrive. Our Employees Are valued and empowered, collaborative and team oriented, innovative in their approach and passionate about their work. They are reliable, trustworthy and open with a high level of integrity. They value diversity, are inclusive and are committed to a global mindset. About the Product Using high-performance DNS services, Global Traffic Manager (GTM) scales and secures your DNS infrastructure during high query volumes and DDoS attacks. It delivers a complete, real-time DNSSEC solution that protects against hijacking attacks. GTM improves the performance and availability of your applications by intelligently directing users to the closest or best-performing physical, virtual, or cloud environment. In addition, enables mitigation of complex threats from malware and viruses by blocking access to malicious IP domains. Position Summary Our team is at the cutting-edge of DNS technology. We are focused on providing customers with solutions to improve access to applications by securing and accelerating Domain Name resolution in hybrid cloud environments. Our team collaborates with other F5 Modular BIG-IP development teams to produce unique opportunities for cross-team development projects. This position is for a Software Engineer III with experience designing and developing application data management software in containerized and orchestrated environments. The engineer will collaborate with software architects and other technical leads to design software and interfaces for our next generation Modular BIG-IP. We are looking for talented software engineers with a track record of accomplishment in the design, implementation and maintenance of major software features. Appropriate candidates should also have a knack for delving into complex deployment configurations and delivering rapid solutions to challenging problems. Responsibilities Develop enterprise grade solutions for the F5 DNS products in containerized and orchestrated environments. Aggressively grow your skillset and expertise to meet the emerging needs of our customers using our new Modular BIG-IP technology Develop and maintain a strong CICD pipeline to efficiently diagnose and resolve critical issues prior to software releases. Work as part of a Scrum team while recommending and maintaining technical design methodologies, processes, and standards Qualifications 3+ year of professional experience in multi-platform network software development, in a commercial production environment. Bachelor degree in computer/engineering related field or equivalent work experience Proven programming skills/abilities in C, C++, and Go Experience with deploying infrastructure and services in one or more cloud environments such as AWS, VMware vSphere, Azure, Google cloud, Practical knowledge of Data Structures, Computer Algorithms and Design Patterns. Development experience in areas such as sockets, multithreading, and data structure optimization. Familiarity with TCP/IP networking a strong plus. Experienced with at least one scripting language such as Python, Perl, Understanding of regexes Development experience using Agile Scrum methodology and Git version control Background in Unix based operating systems specifically, x86/Linux Strong problem-solving and analytical skills Proven ability to deliver products with highest quality and on time Strong written and verbal communications skills Ability to interact and communicate effectively with users of our products. The About The Role is intended to be a general representation of the responsibilities and requirements of the job. However, the description may not be all-inclusive, and responsibilities and requirements are subject to change. Please note that F5 only contacts candidates through F5 email address (ending with @f5.com) or auto email notification from Workday (ending with f5.com or @myworkday.com ) . Equal Employment Opportunity It is the policy of F5 to provide equal employment opportunities to all employees and employment applicants without regard to unlawful considerations of race, religion, color, national origin, sex, sexual orientation, gender identity or expression, age, sensory, physical, or mental disability, marital status, veteran or military status, genetic information, or any other classification protected by applicable local, state, or federal laws. This policy applies to all aspects of employment, including, but not limited to, hiring, job assignment, compensation, promotion, benefits, training, discipline, and termination. F5 offers a variety of reasonable accommodations for candidates . Requesting an accommodation is completely voluntary. F5 will assess the need for accommodations in the application process separately from those that may be needed to perform the job. Request by contacting accommodations@f5.com.

At F5, we strive to bring a better digital world to life. Our teams empower organizations across the globe to create, secure, and run applications that enhance how we experience our evolving digital world. We are passionate about cybersecurity, from protecting consumers from fraud to enabling companies to focus on innovation. Everything we do centers around people. That means we obsess over how to make the lives of our customers, and their customers, better. And it means we prioritize a diverse F5 community where each individual can thrive. Our Employees Are valued and empowered, collaborative and team oriented, innovative in their approach and passionate about their work. They are reliable, trustworthy and open with a high level of integrity. They value diversity, are inclusive and are committed to a global mindset. About the Product Using high-performance DNS services, Global Traffic Manager (GTM) scales and secures your DNS infrastructure during high query volumes and DDoS attacks. It delivers a complete, real-time DNSSEC solution that protects against hijacking attacks. GTM improves the performance and availability of your applications by intelligently directing users to the closest or best-performing physical, virtual, or cloud environment. In addition, enables mitigation of complex threats from malware and viruses by blocking access to malicious IP domains. Position Summary Our team is at the cutting-edge of DNS technology. We are focused on providing customers with solutions to improve access to applications by securing and accelerating Domain Name resolution in hybrid cloud environments. Our team collaborates with other F5 Modular BIG-IP development teams to produce unique opportunities for cross-team development projects. This position is for a Senior Software Engineer with strong experience designing and developing application data management software in containerized and orchestrated environments. The engineer will collaborate with software architects and other technical leads to design software and interfaces for our next generation Modular BIG-IP. We are looking for talented software engineers with a track record of accomplishment in the design, implementation and maintenance of major software features. Appropriate candidates should also have a knack for delving into complex deployment configurations and delivering rapid solutions to challenging problems. Responsibilities Develop enterprise grade solutions for the F5 DNS products in containerized and orchestrated environments. Aggressively grow your skillset and expertise to meet the emerging needs of our customers using our new Modular BIG-IP technology Define, collect and interpret product and system requirements to design, implement and maintain software solutions to meet our customer needs. Develop and maintain a strong CICD pipeline to efficiently diagnose and resolve critical issues prior to software releases. Work as part of a Scrum team while recommending and maintaining technical design methodologies, processes, and standards Provide technical mentorship to lower level engineers Qualifications 6+ year of professional experience in multi-platform network software development, in a commercial production environment. Bachelor degree in computer/engineering related field or equivalent work experience Proven programming skills/abilities in C, C++, and Go Strong xxperience with deploying infrastructure and services in one or more cloud environments such as AWS, VMware vSphere, Azure, Google cloud, Strong development experience in areas such as sockets, multithreading, and data structure optimization. Familiarity with TCP/IP networking a strong plus. Experienced with at least one scripting language such as Python, Perl, Understanding of regexes Development experience using Agile Scrum methodology and Git version control Background in Unix based operating systems specifically, x86/Linux Strong problem-solving and analytical skills paired with strong mentorship experience Proven ability to deliver products with highest quality and on time Strong written and verbal communications skills Ability to interact and communicate effectively with users of our products The About The Role is intended to be a general representation of the responsibilities and requirements of the job. However, the description may not be all-inclusive, and responsibilities and requirements are subject to change. Please note that F5 only contacts candidates through F5 email address (ending with @f5.com) or auto email notification from Workday (ending with f5.com or @myworkday.com ) . Equal Employment Opportunity It is the policy of F5 to provide equal employment opportunities to all employees and employment applicants without regard to unlawful considerations of race, religion, color, national origin, sex, sexual orientation, gender identity or expression, age, sensory, physical, or mental disability, marital status, veteran or military status, genetic information, or any other classification protected by applicable local, state, or federal laws. This policy applies to all aspects of employment, including, but not limited to, hiring, job assignment, compensation, promotion, benefits, training, discipline, and termination. F5 offers a variety of reasonable accommodations for candidates . Requesting an accommodation is completely voluntary. F5 will assess the need for accommodations in the application process separately from those that may be needed to perform the job. Request by contacting accommodations@f5.com.

At F5, we strive to bring a better digital world to life. Our teams empower organizations across the globe to create, secure, and run applications that enhance how we experience our evolving digital world. We are passionate about cybersecurity, from protecting consumers from fraud to enabling companies to focus on innovation. Everything we do centers around people. That means we obsess over how to make the lives of our customers, and their customers, better. And it means we prioritize a diverse F5 community where each individual can thrive. About The Role : F5 Networks – Hyderabad, India Our Employees Are valued and empowered, collaborative and team oriented, innovative in their approach and passionate about their work. They are reliable, trustworthy and open with a high level of integrity. They value diversity, are inclusive and are committed to a global mindset. About the Product Using high-performance DNS services, Global Traffic Manager (GTM) scales and secures your DNS infrastructure during high query volumes and DDoS attacks. It delivers a complete, real-time DNSSEC solution that protects against hijacking attacks. GTM improves the performance and availability of your applications by intelligently directing users to the closest or best-performing physical, virtual, or cloud environment. In addition, enables mitigation of complex threats from malware and viruses by blocking access to malicious IP domains. Position Summary Our team is at the cutting-edge of DNS technology. We are focused on providing customers with solutions to improve access to applications by securing and accelerating Domain Name resolution in hybrid cloud environments. Our team collaborates with other F5 Modular BIG-IP development teams to produce unique opportunities for cross-team development projects. This position is for a Software Engineer III with experience designing and developing application data management software in containerized and orchestrated environments. The engineer will collaborate with software architects and other technical leads to design software and interfaces for our next generation Modular BIG-IP. We are looking for talented software engineers with a track record of accomplishment in the design, implementation and maintenance of major software features. Appropriate candidates should also have a knack for delving into complex deployment configurations and delivering rapid solutions to challenging problems. Responsibilities Develop enterprise grade solutions for the F5 DNS products in containerized and orchestrated environments. Aggressively grow your skillset and expertise to meet the emerging needs of our customers using our new Modular BIG-IP technology Develop and maintain a strong CICD pipeline to efficiently diagnose and resolve critical issues prior to software releases. Work as part of a Scrum team while recommending and maintaining technical design methodologies, processes, and standards Qualifications 3+ year of professional experience in multi-platform network software development, in a commercial production environment. Bachelor degree in computer/engineering related field or equivalent work experience Proven programming skills/abilities in C, C++, and Go Experience with deploying infrastructure and services in one or more cloud environments such as AWS, VMware vSphere, Azure, Google cloud, Practical knowledge of Data Structures, Computer Algorithms and Design Patterns. Development experience in areas such as sockets, multithreading, and data structure optimization. Familiarity with TCP/IP networking a strong plus. Experienced with at least one scripting language such as Python, Perl, Understanding of regexes Development experience using Agile Scrum methodology and Git version control Background in Unix based operating systems specifically, x86/Linux Strong problem-solving and analytical skills Proven ability to deliver products with highest quality and on time Strong written and verbal communications skills Ability to interact and communicate effectively with users of our products Physical Demands and Work Environment Daily computer use in an office environment. Occasional need to install computer equipment in racks and replace existing equipment. Equipment includes servers, routers, power supplies, and network appliances. Benefits: We provide competitive salaries, a world class benefits package, including 100% of the premium for employee medical, dental and vision insurance, highly subsidized premiums for dependent coverage, 401K match, employees stock purchase plan, 18 days paid time off within the 1st year and 9 paid holidays, life insurance, short & long term disability insurance, tuition reimbursement, and much more. The About The Role is intended to be a general representation of the responsibilities and requirements of the job. However, the description may not be all-inclusive, and responsibilities and requirements are subject to change. Please note that F5 only contacts candidates through F5 email address (ending with @f5.com) or auto email notification from Workday (ending with f5.com or @myworkday.com ) . Equal Employment Opportunity It is the policy of F5 to provide equal employment opportunities to all employees and employment applicants without regard to unlawful considerations of race, religion, color, national origin, sex, sexual orientation, gender identity or expression, age, sensory, physical, or mental disability, marital status, veteran or military status, genetic information, or any other classification protected by applicable local, state, or federal laws. This policy applies to all aspects of employment, including, but not limited to, hiring, job assignment, compensation, promotion, benefits, training, discipline, and termination. F5 offers a variety of reasonable accommodations for candidates . Requesting an accommodation is completely voluntary. F5 will assess the need for accommodations in the application process separately from those that may be needed to perform the job. Request by contacting accommodations@f5.com.