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Posted:3 days ago| Platform: Linkedin logo

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Skills Required

design verilog systemverilog architecture interface usb ethernet synopsys cadence siemens compiler power dft linting synthesis timing documentation collaboration ai ml software electrical

Work Mode

On-site

Job Type

Full Time

Job Description

Role Description:


Exp:


Location:


  • Experience:

    8–10 years in VLSI Frontend & RTL Design, with at least one complete

    end-to-end SoC development

    ownership.

  • Strong RTL Design Expertise:

    Verilog, SystemVerilog, VHDL.

  • Micro-architecture Design:

    Experience defining and implementing high-performance compute or control-intensive SoC subsystems.

  • Interface & Protocol Knowledge:

    AMBA (AXI/AHB/APB), PCIe, DDR, USB, MIPI, I2C/SPI, Ethernet, etc.

  • EDA Tools:

    Synopsys/Cadence/Siemens front-end tools (Design Compiler, Spyglass, VCS, Incisive, etc.).

  • Power-aware Design Techniques:

    Clock gating, multi-Vt, UPF/CPF based design.
  • Good understanding of

    DFT, CDC, Linting, Synthesis constraints

    , timing closure.
  • Exposure to

    RISC-V/ARM architecture

    , cache design, coherency protocols, and IO subsystems.
  • Strong documentation skills, design reviews, and collaboration in cross-functional teams.
  • Experience with

    AI/ML accelerators

    , Automotive/ADAS SoCs, or high-speed SerDes. (Good to have)
  • Knowledge of

    High-Level Synthesis (HLS)

    flows and SystemC modeling.
  • Familiarity with firmware/embedded software and driver bring-up.


Educational Qualification:

  • B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, VLSI, or equivalent from a reputed institute.

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