Technical Lead I - VLSI DFT

Role Overview: You will be independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, your responsibility will include owning a task in RTL Design/Module and providing support and guidance to engineers in various areas like Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Anticipating, diagnosing, and resolving problems by coordinating with cross-functional teams to ensure on-time quality delivery approved by the project manager and client will be crucial. Key Responsibilities: - Automate design tasks flows and write scripts to generate reports - Come up with innovative ideas to reduce design cycle time and cost - Ensure quality verification and timely delivery - Contribute to reduction in cycle time cost through innovative approaches - Publish papers, file patents, and attend mandatory trainings - Ensure zero bugs in the design and clean delivery of the design/module for easy integration - Meet functional specifications and design guidelines without deviation - Document tasks and work performed - Deliver tasks on time to meet project timelines - Support team progress by delivering intermediate tasks - Participate in team activities and support team members - Mentor junior team members Qualifications Required: - Proficiency in languages like System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK - Experience with EDA tools like Cadence, Synopsys, Mentor tool sets, simulators - Technical knowledge in IP Spec, Bus Protocols, Physical Design, Synthesis, DFT - Strong communication, analytical reasoning, and problem-solving skills - Attention to detail and ability to understand specs and functional documents - Familiarity with EDA tools and willingness to learn new skills - Prior design knowledge - Experience in DFT ATPG, Mbist, SCAN, and knowledge of SOC or Subsystems designs - Knowledge of DFT methodologies, low power design practices, scan methodologies, ATPG, MBIST, JTAG implementation, and test mode timing constraint development would be advantageous,