Technical Lead I - VLSI DFT

The role involves independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will be responsible for owning a task in RTL Design/Module and providing support and guidance to engineers in various areas like Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will need to anticipate, diagnose, and resolve problems by coordinating with cross-functional teams, ensuring on-time quality delivery approved by the project manager and client. One of the key aspects of the role is to automate design tasks flows and write scripts to generate reports while also coming up with innovative ideas to reduce design cycle time and cost, which should be accepted by the UST Manager and client. Measures of success will include quality verification, timely delivery, reduction in cycle time cost through innovative approaches, number of papers published, number of patents filed, and attending mandatory trainings to meet training goals. The expected outputs include ensuring zero bugs in the design, clean delivery of the design/module for easy integration at the top level, meeting functional specifications and design guidelines without deviation, and documenting tasks and work performed. Timely delivery is crucial, meeting project timelines set by the client or program manager, delivering intermediate tasks to enable team progress, and seeking help and support in case of task delays. Continuous skill development is encouraged through participation in training, skilling others, acquiring new technologies, and taking up new areas of project development. Teamwork is essential, involving participation in team activities, supporting team members, taking up additional tasks when needed, and mentoring junior team members. Innovation and creativity are valued, with a focus on automating tasks to save design cycle time, participating in technical discussions, training, forums, white papers, etc. Skills required include proficiency in languages like System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and EDA tools like Cadence, Synopsys, Mentor tool sets, simulators, and technical knowledge in IP Spec, Bus Protocols, Physical Design, Synthesis, DFT, etc. Strong communication, analytical reasoning, problem-solving skills, attention to detail, ability to understand specs and functional documents, and deliver tasks on time with quality are essential. Familiarity with EDA tools, willingness to learn new skills, and prior design knowledge are also necessary for successful project execution. Experience in DFT ATPG, Mbist, SCAN, and knowledge of SOC or Subsystems designs, DFT methodologies, low power design practices, scan methodologies, ATPG, MBIST, JTAG implementation, and test mode timing constraint development will be advantageous for the role.,