2 Dft Atpg Jobs

You will be expected to independently execute mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will own a specific task related to RTL Design/Module and provide support and guidance to engineers in various areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Your role will involve anticipating, diagnosing, and resolving problems while coordinating with cross-functional teams as necessary. It is essential to ensure on-time quality delivery that meets the approval of the project manager and the client. Additionally, you will be responsible for automating design tasks flows, writing scripts to generate reports, and proposing innovative ideas to reduce design cycle time and cost, which should be accepted by UST Manager and the client. Your performance will be measured based on the quality of deliverables, timely delivery, reduction in cycle time and cost through innovative approaches, the number of papers published, the number of patents filed, and the number of mandatory trainings attended. You should aim to deliver high-quality work by ensuring zero bugs in the design/circuit design, clean delivery of the design/module for easy integration at the top level, meeting functional specifications/design guidelines without any deviation, and documenting tasks and work performed. Timely delivery is crucial, and you must adhere to project timelines, deliver intermediate tasks to support team progress, and seek help and support if there are delays in task delivery. Continuous skills development is encouraged through participation in training sessions, upskilling in newer technologies, and taking on new areas of project development to enhance your knowledge and deliver results. Teamwork is essential, and you should actively participate, support team members when needed, take on additional tasks in the absence of team members, and assist junior team members in understanding project tasks. Going beyond the call of duty to meet deadlines and maintain quality standards is expected. Innovation and creativity are valued, and you should automate tasks to save design cycle time, participate in technical discussions, training forums, and contribute to white papers. Your skills should include proficiency in languages and programming such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. Experience with EDA tools like Cadence, Synopsys, Mentor tool sets, simulators, and various technical knowledge areas is required. Strong communication, analytical reasoning, problem-solving skills, attention to detail, and the ability to deliver tasks on time are essential. You should be well-versed in EDA tools, have the necessary technical skills, and be willing to learn new skills as required for project execution. Knowledge of project execution in various design areas, understanding design flow and methodologies, and the ability to execute project tasks as per known skills are key. Specific experience in DFT ATPG, Mbist, and SCAN is preferred, along with expertise in SOC or Subsystems designs, DFT methodologies, and standard DFT tools. Familiarity with SoC style DFT architectures, low power design practices, test mode timing constraint development, and analysis will be beneficial. Hands-on experience in ATPG, SCAN, MBIST, JTAG implementation, and knowledge of test compression and ATE debug are valuable assets. Your role will involve utilizing your skills and knowledge to contribute effectively to project success.,

The role involves independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will be responsible for owning a task in RTL Design/Module and providing support and guidance to engineers in various areas like Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will need to anticipate, diagnose, and resolve problems by coordinating with cross-functional teams, ensuring on-time quality delivery approved by the project manager and client. One of the key aspects of the role is to automate design tasks flows and write scripts to generate reports while also coming up with innovative ideas to reduce design cycle time and cost, which should be accepted by the UST Manager and client. Measures of success will include quality verification, timely delivery, reduction in cycle time cost through innovative approaches, number of papers published, number of patents filed, and attending mandatory trainings to meet training goals. The expected outputs include ensuring zero bugs in the design, clean delivery of the design/module for easy integration at the top level, meeting functional specifications and design guidelines without deviation, and documenting tasks and work performed. Timely delivery is crucial, meeting project timelines set by the client or program manager, delivering intermediate tasks to enable team progress, and seeking help and support in case of task delays. Continuous skill development is encouraged through participation in training, skilling others, acquiring new technologies, and taking up new areas of project development. Teamwork is essential, involving participation in team activities, supporting team members, taking up additional tasks when needed, and mentoring junior team members. Innovation and creativity are valued, with a focus on automating tasks to save design cycle time, participating in technical discussions, training, forums, white papers, etc. Skills required include proficiency in languages like System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and EDA tools like Cadence, Synopsys, Mentor tool sets, simulators, and technical knowledge in IP Spec, Bus Protocols, Physical Design, Synthesis, DFT, etc. Strong communication, analytical reasoning, problem-solving skills, attention to detail, ability to understand specs and functional documents, and deliver tasks on time with quality are essential. Familiarity with EDA tools, willingness to learn new skills, and prior design knowledge are also necessary for successful project execution. Experience in DFT ATPG, Mbist, SCAN, and knowledge of SOC or Subsystems designs, DFT methodologies, low power design practices, scan methodologies, ATPG, MBIST, JTAG implementation, and test mode timing constraint development will be advantageous for the role.,