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SV/UVM Lead

SV/UVM Lead

Coventine Digital

5 - 10 years

|

3 - 8 Lacs

Hyderabad Bengaluru

Posted:1 month ago| Platform:

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Skills Required

Sv DDR SOC Verification PCIe UVM Ethernet GLS

Work Mode

Work from Office

Job Type

Full Time

Job Description

Roles and Responsibilities

Design verification using UVM (Universal Verification Methodology) for PCIe, DDR, Ethernet interfaces on SOCs.
Develop test benches in System Verilog for verifying complex digital designs.
Collaborate with cross-functional teams to identify requirements and develop test plans.
Utilize GLS (Golden Labs Simulation) tools for simulation setup and debugging.
Participate in peer reviews to ensure high-quality deliverables. Must have good debugging skills.
Experience in any of the slow speed peripherals like I2C, SPI, UART is a plus.

Desired Candidate Profile

5 years of experience in SV/UVM Lead role with expertise in design verification using UVM methodology.
Bachelor's degree (B.Tech/B.E.).
Master's degree preferred but not mandatory (M.Tech).
Strong understanding of SystemVerilog programming language and its application in DV testing.

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