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Staff IP Design Verification CXL

4 - 8 years

4 - 8 Lacs

Bengaluru / Bangalore Karnataka India

Posted:5 days ago| Platform: Foundit logo

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Skills Required

Uvm systemverilog PCIe/CXL/AXI Coverage Closure SVA

Work Mode

On-site

Job Type

Full Time

Job Description

Own and develop UVM-based testbench environments for IP/SoC verification Design verification architecture, testplans, and SVA based on protocol specifications (PCIe, CXL, UCIe, AXI, etc.) Drive all aspects of the verification lifecycle including testbench creation, coverage closure, and debugging Collaborate with RTL design teams to resolve issues and close functional coverage Conduct peer reviews to maintain high testbench code quality Contribute technical papers and patent ideas on testbench innovations and verification methodologies Work closely with global teams and ensure timely project execution The Impact You Will Have: Deliver reliable and robust verification solutions that ensure high-quality IP/SoC design Influence UVM testbench architecture through innovation and best practices Improve efficiency and accuracy in verification through SVA and advanced debugging Enable faster time-to-market by streamlining simulation and debug processes Contribute to Synopsys IP leadership by ensuring verification excellence across global projects What You'll Need: 48 years of experience in UVM-based verification for IP/SoC Strong SystemVerilog knowledge and protocol understanding (PCIe, CXL, UCIe, AXI, etc.) Hands-on experience with functional coverage closure and SystemVerilog Assertions (SVA) Proficiency in simulation tools and waveform debug tools like DVE/Verdi Familiarity with version control tools (e.g., Perforce) Scripting knowledge (Python, TCL) is an added advantage Strong communication, problem-solving skills, and ability to work across teams and geographies

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