5 - 10 years

50 - 55 Lacs

Posted:20 hours ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

  • Define and drive netlist-level power estimation methodologies using industry-leading tools (e.g., Synopsys PrimeTime PX, Cadence Voltus).
  • Establish and maintain correlation frameworks between RTL and gate-level power, and between estimated and silicon power.
  • Develop automated flows for toggling activity generation, vector-based and vectorless power estimation, and regression reporting.
  • Analyze power consumption trends and identify hotspots; provide recommendations for low-power design optimization.
  • Collaborate with RTL design, physical design, DFT, and architecture teams to ensure early and accurate power signoff.
  • Lead methodology development for corner analysis, dynamic/static power separation, and voltage scaling assessments.
  • Support signoff reviews, audits, and compliance to power specifications and constraints.
  • Provide mentorship and technical leadership within the team and across global sites

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ARM Embedded Technologies

Technology / Embedded Systems

San Jose

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