STA Lead

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THE ROLE:

This exciting position as MTS in AMD's Silicon IP solutions & SOC group will provide the individual with an opportunity to demonstrate strong technical leadership across the design hierarchy from architecture to Productization. Join us in providing innovative IP solutions as we embark on our journey into the cutting edge programmable logic based silicon designs by delivering the complex IP Solutions for multiple market segments

As part of this opportunity, we are seeking a Synthesis and Timing engineer to participate in the development of large SOC's with multiple physical blocks and 300+ clock domains.

This position requires an individual to be creative, team-oriented, technology savvy, able to lead large cross-functional teams, comfortable and willing to provide regular updates to management chain during the project execution

THE PERSON:

You have a passion for modern, complex hardware and IP architecture, digital design, and physical design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff
• Drive the effort to maintain RTL quality metrics in complex, hierarchical designs and automating that process for improved efficiency.
• Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks
• Work with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) flows
• Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts)

PREFERRED EXPERIENCE:

• About 6 to 10 years of relevant experience
• Worked with EDA tools that enable RTL quality checks
• Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
• Experience with analyzing the timing reports and identifying both the design and constraints related issues.
  Ability to multitask and grasp new flows/tools/ideas
• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc
• Automating workflows in a distributed compute environment.
• Scripting language experience: Python/TCL preferred.

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

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Benefits offered are described: .

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.