STA Engineer

As a Static Timing Analysis (STA) Engineer at Incise Infotech Limited in Noida, you will be a key contributor to the VLSI Design team, working on high-performance chip design projects. Your role will involve performing STA at block and full-chip levels using tools such as PrimeTime or Tempus. You will analyze and debug timing violations, collaborate with RTL, Synthesis, and Physical Design teams for timing closure, and develop SDC constraints for various design stages. Your expertise in timing concepts, clock domains, and signal integrity will be crucial for ensuring timing sign-off readiness and supporting tape-out schedules. Additionally, you will innovate and automate STA flows, support PPA analysis, and provide inputs during design reviews for multiple projects. To excel in this role, you should have hands-on experience with STA tools, a strong understanding of timing concepts, and expertise in writing and debugging SDC constraints. Your solid knowledge of CMOS, VLSI design flows, and timing closure methodologies will be essential. Proficiency in TCL scripting, familiarity with synthesis and physical design interactions, and experience with advanced technology nodes like 7nm, 16nm, or 28nm will be advantageous. Good communication, problem-solving skills, and the ability to work both independently and collaboratively in a fast-paced environment are also required. If you are a passionate engineer looking to contribute to full-chip timing closure, constraint development, and timing verification in advanced technology nodes, this role offers an exciting opportunity to drive innovation and quality in chip design projects at Incise Infotech Limited.,