Sr. Staff Verification Expert (CXL IP Design)

Job Description

BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI, APB, AHB) etc Good knowledge of System Verilog Hands-on experience with coverage closure and writing SVA for IP/SOC Good simulation debugging skills Experience with Perforce or similar revision control environment Experience with Python/TCL or any scripting knowledge is an added advantage Job Responsibilities include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification Be single point of contact with hands-on experience on all verification tasks Testbench Creation Testplan creation Coverage closure SVA Release Perform peer review of testbench code for continuous quality Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide Lead team of engineers to perform various verification activities on IPs/Subsystems Anticipate problems and risks and work towards a resolution and risk mitigation plan Assist and mentor the team in day-to-day activities and grow the capabilities of verification team for future assignments Review various results and reports to provide continuous feedback to the team and improve quality of deliverables Report status to management and provide suggestions to resolve any issues that may impact execution The candidate must have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative