Senior/Lead Asic Verification Engineer (VIP Development - PCIE/MIPI/Ethernet/UCIe/USB)

Senior/Lead ASIC Verification Engineers

• Experience : 5yrs to 15 years (multiple roles)

• Location:

  Noida

• Associated with Verification especially using industry-standard protocols & methodology
• Languages: Hands-on experience with

  System Verilog & Verilog

  . Should have a good understanding of Object Oriented Programming.
• Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using

  VMM/OVM/UVM methodologies

  .
• Protocol experience:

  Should have experience on any of the UCIe/PCIe/CXL/Unipro/USB/MIPI/HDMI/Ethernet/DDR/LPDDR/HBM memory protocol

• Job responsibilities:
• Able to contribute to the development of the VIP
• Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective.
• Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective

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• Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.