Senior Physical Verification Engineer

5 - 9 years

0 Lacs

Posted:5 days ago| Platform: Shine logo

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Work Mode

On-site

Job Type

Full Time

Job Description

As a Physical Verification Engineer for SOC/blocks, your role will involve the following key responsibilities: - Conduct physical verification for SOCs, cores, and blocks, encompassing tasks such as DRC, LVS, ERC, ESD, DFM, and tapeout processes. - Tackle critical design and execution challenges related to physical verification and sign-off. - Possess a thorough understanding of physical verification and sign-off workflows and methodologies. - Collaborate with PNR engineers to attain sign-off at different stages of the design process. To excel in this role, you should have the following qualifications and skills: - Proficiency in physical verification for SoC/full-chip and block-level processes, covering DRC, LVS, ERC/PERC, DFM, OPC, and tapeout. - Extensive experience and comprehension of all phases of the IC design process from RTL to GDS2. - Ability to troubleshoot LVS issues at the chip level, particularly concerning complex analog-mixed signal IPs. - Knowledge of low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation. - Hands-on experience in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components. - Proficiency in developing sign-off methodologies/flows and providing support to larger teams. - Understanding of ERC rules, PERC rules, and ESD rules is considered a valuable asset. - Experience in floorplanning would be advantageous.,

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