3 Rdl Routing Jobs

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems in order to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. This position is focused on floor-planning expertise at both block and top levels for industry-leading CPU core designs, emphasizing scalability and achieving aggressive Power, Performance, and Area (PPA) targets. Working on cutting-edge technology nodes and applying advanced physical design techniques to enhance CPU performance and efficiency is a key aspect of this role. Key responsibilities include driving floorplan architecture and optimization in collaboration with PD/RTL teams, engaging in cross-functional collaboration with Physical design, timing, power, and packaging teams, partnering with EDA tool vendors and internal CAD teams for improved design efficiency, making strategic trade-offs in design decisions to achieve optimal PPA outcomes, and ensuring end-to-end Physical verification closure for subsystem. The ideal candidate will have experience in physical design including floor-planning, placement, clock implementation, and routing for complex, big, and high-speed designs. Knowledge of physical synthesis and implementation tools such as Cadence Innovus/Genus and Synopsys Fusion Compiler is preferred, along with a good understanding of CMOS circuit design, static timing analysis, reliability, and power analysis. Strong collaboration skills, innovative thinking for power and performance improvements, scripting skills, and expertise in Physical Verification flow are required. Preferred skills for this role include clock implementation, power delivery network design choices, process technology knowledge, experience in flow and methodology development, hands-on experience with Synthesis, DFT, Place and Route, and Timing and Reliability Signoff. Interaction with design and architecture teams, working with sub-micron technology process nodes, and prior experience in flow and methodology development are advantageous. Minimum qualifications include a Bachelor's degree in Electrical/Computer Engineering, 8+ years of direct top-level floor-planning experience, a strong background in VLSI design, physical implementation, and scripting, as well as experience working with industry-standard Synthesis and Place and Route tools. Self-motivation, time management skills, and a commitment to abide by all applicable policies and procedures are expected from applicants. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes. For more information about this role, please contact Qualcomm Careers.,

Foundry Services (FS) is an independent foundry business established to meet customers" unique product needs. With the first Open System Foundry model globally, combined offerings include wafer fabrication, advanced process, packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities. This helps customers build innovative silicon designs and deliver customizable products from Intel's secure, resilient, and sustainable supply source. This job opportunity in FS will be part of the Customer Solutions Engineering (CSE) group, responsible for bringing the best of Intel technologies to FS customers, accelerating solutions from architecture to post-silicon validation. We are seeking an experienced Floorplan Engineer to focus on floor plan, die estimation, and power planning for high-performance designs. Responsibilities include establishing integration plans for die with optimization for package and board constraints, bump planning, die file generation, collaborating with architects for IP or SoC placement optimization, clocking and dataflow collaboration, deriving specifications for IP blocks, coordinating with power delivery team, maximizing die-per-reticle/good-die-per-wafer, RDL routing knowledge, and package integration before tape-out. **Qualifications:** - 12+ years of experience after a Bachelor or Master of Engineering degree in Electrical/Electronic/VLSI Engineering or related field. - Led multiple SOCs as SOC Floorplan lead, expertise in design planning, die estimation, knowledge of clocking, high-speed design signal routing, industry protocols, IP architecture, library/memory/technology/submicron issues. - Strong teamwork, flexibility, ability to thrive in a dynamic environment. **Job Type:** Experienced Hire **Shift:** Shift 1 (India) **Primary Location:** India, Bangalore Intel Foundry is committed to transforming the global semiconductor industry by providing cutting-edge silicon process and packaging technology. Innovating under Moore's Law, fostering collaboration, and investing in geographically diverse manufacturing capacities. Intel Foundry enables the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, dedicated to customer success with full P&L responsibilities.,

Description The Bonding/RDL Routing/Package Interface role is crucial for developing innovative packaging solutions in the semiconductor industry. The candidate will be responsible for designing and optimizing bonding and routing strategies, ensuring effective integration of package interfaces, and collaborating with various teams to deliver high-quality products. Responsibilities Design and optimize bonding and routing strategies for advanced packaging solutions. Collaborate with cross-functional teams to ensure seamless package interface integration. Analyze and troubleshoot issues related to RDL routing and bonding processes. Develop and maintain documentation for bonding and routing methodologies and best practices. Conduct testing and validation of package interfaces to ensure reliability and performance. Skills and Qualifications Bachelor's degree in Electrical Engineering, Electronics, or a related field. Strong understanding of semiconductor packaging processes and materials. Proficiency in CAD tools for layout design and simulation (e.g., Cadence, Mentor Graphics). Experience with RDL (Re-distribution Layer) design and bonding techniques. Knowledge of electrical and thermal performance analysis for package interfaces. Familiarity with IPC standards related to electronic packaging.