12 Rdl Routing Jobs

5+ Years Able to make IO Ring and RDL routing. • Should have good hands on of Clock Tree Synthesis using Innovus. • Should be able to perform EMIR analysis with Ansys Redhawk. • Should be able to perform Physical Verification with Calibre

As a Physical Design Engineer at Kinara, your role involves the following responsibilities: - Physical Design of complex data path and control blocks - Developing new techniques and flows to rapidly prototype hardware blocks - Developing flows that allow for detailed power estimation - Working with the design team to understand placement and recommend implementation options - Interacting and engaging with external teams to drive as well as deliver subsystems leading to chip tapeout Preferred qualifications for this position include: - BTech/MTech EE/CS with 8+ Years of Physical Design experience - Extensive knowledge of Automated synthesis, Technology mapping, Place-and-Route, and Layout tec...

As a Physical Verification Engineer for SOC/blocks, your role will involve the following key responsibilities: - Conduct physical verification for SOCs, cores, and blocks, encompassing tasks such as DRC, LVS, ERC, ESD, DFM, and tapeout processes. - Tackle critical design and execution challenges related to physical verification and sign-off. - Possess a thorough understanding of physical verification and sign-off workflows and methodologies. - Collaborate with PNR engineers to attain sign-off at different stages of the design process. To excel in this role, you should have the following qualifications and skills: - Proficiency in physical verification for SoC/full-chip and block-level proces...

Role : Sr Physical Design Lead/BE Integration This position is for senior level engineer Full Chip Physical Design/Integrations/ SoC Floor planning/Bump Planning/ Pin Assignments /Feed through/ LFU Optimization/Physical Verification, Power design/implementation/signoff. He must have hands on Physical Design experience and must have handled RTL to GDS II at Top level Key Responsibilities: Expertise in hierarchical RTL2GDSII design implementation Expertise in pin assignment, Power planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps Full chip Hierarchical Floor Planning, Block planning , block level constraints, hierarc...

Were Hiring: Physical Design Engineer Location: Bangalore, India Experience: 5+ Years Key Responsibilities: Create IO Ring and RDL routing Perform Clock Tree Synthesis (CTS) using Cadence Innovus Conduct EMIR analysis with Ansys Redhawk Execute Physical Verification using Calibre Requirements: Strong understanding of physical design flow & methodologies Excellent problem-solving and debugging skills Ability to thrive in a fast-paced, collaborative environment Apply Now: Send your resume to surapandey@allegisglobalsolutions.com

Who we are Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz (http://www-vlsi.stanford.edu/horowitz/) and Prof. Christos Kozyrakis (http://csl.stanford.edu/christos/). What we do Our game-changing AI solutions revolutionize what people and businesses can achieve. Ara inference processors combined with our SDK deliver unrivaled deep learning performance at the edge to accelerate and optimize real-time decision making where every millisecond is critical, and power efficiency is a must. Kinara solutions embed high-performance AI into edge devi...

As a Physical Verification Engineer for SOC/blocks, your role involves performing physical verification for SOCs, cores, and blocks, which includes tasks such as DRC, LVS, ERC, ESD, DFM, and tapeout processes. You will be responsible for addressing critical design and execution challenges related to physical verification and sign-off. It is essential for you to have a comprehensive understanding of physical verification and sign-off workflows and methodologies. Collaboration with PNR engineers to achieve sign-off at various stages of the design process is also a key aspect of your role. Your qualifications and skills should include proficiency in physical verification for SoC/full-chip and b...

Physical Design Lead / Manager Bangalore, India Minimum of 10 + years experience in SoC Physical Design experience with Bachelor of Engineering and/or MS Educational Qualification. Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Good hands on experience in Hierarchical designs implementation methodologies Must have detailed knowledge on Die size estimate, Floorplan and partition strategies for Low power designs for best PPA. Bump planning, working with Packaging team and RDL routing experience is must. Design, Constraints and DFT along with PD planning must be handled by PD lead. CAD, Methodology & IP team collaboration i...

Role Overview: As a Qualcomm Hardware Engineer at Qualcomm India Private Limited, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. This position will focus on floor-planning expertise at both block and top levels for industry-leading CPU core designs, with an emphasis on scalability and achieving aggressive Power, Performance, and Area (PPA) targets. Key Responsibilities: - Drive floorplan architecture and optimization in collaboration with PD/RTL teams to maximize PPA - Engage in cross-fun...

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems in order to launch cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. This position is focused on floor-planning expertise at both block and...

Foundry Services (FS) is an independent foundry business established to meet customers" unique product needs. With the first Open System Foundry model globally, combined offerings include wafer fabrication, advanced process, packaging technology, chiplet, software, robust ecosystem, and assembly and test capabilities. This helps customers build innovative silicon designs and deliver customizable products from Intel's secure, resilient, and sustainable supply source. This job opportunity in FS will be part of the Customer Solutions Engineering (CSE) group, responsible for bringing the best of Intel technologies to FS customers, accelerating solutions from architecture to post-silicon validati...

Description The Bonding/RDL Routing/Package Interface role is crucial for developing innovative packaging solutions in the semiconductor industry. The candidate will be responsible for designing and optimizing bonding and routing strategies, ensuring effective integration of package interfaces, and collaborating with various teams to deliver high-quality products. Responsibilities Design and optimize bonding and routing strategies for advanced packaging solutions. Collaborate with cross-functional teams to ensure seamless package interface integration. Analyze and troubleshoot issues related to RDL routing and bonding processes. Develop and maintain documentation for bonding and routing meth...