Senior Lead - SOC Design Verification

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SMTS SILICON DESIGN ENGINEER

THE ROLE (SOC Verification Lead):

• Drive and lead the SOC level verification activities for entire SOC. Across domains.
• Work with customer on feature requirements, use case scenarios, test plan reviews to realize the SOC is meeting all functional aspects of the targeted domain after integrating the IP s.
• Work with architecture and design team on high level arch, Integration, use case scenarios, config space etc. Work with IP team for IP Integration, IP requirement and deliverables.
• Work with vendors and ODC members for the successful project execution
• Work with program management team for SOC planning, schedule, resource demand/supply, critical path analysis and execution.

THE PERSON:

• Leader with strong self-driving ability
• Need excellent communication skills (both written and oral)
• Strong problem-solving skills, go to person for SOC verification / Concurrency / Coherency / Consistency / System level understanding/IP deployment/integration activities/ARM Subsystem/X86 Cores/ NOC/Trustzones/Security aspects/Boot.

KEY RESPONSIBILITIES:

• Leading SOC verification, has knowledge of domains across full SOC.
• Running regular execution meetings and scrums to resolve bottlenecks with team.
• Project planning including schedule, deliverables, risk identification and mitigations options.
• Drive the team for the bug free silicon deliverable and increase the efficiency by adapting the possible automation in the environment.

PREFERRED EXPERIENCE:

• Global data path verification, Core data path verification, Security veirifcation, trustzones, NOCs and coherency across fabric.
• Expertise in IP, Subsystem and SOC Verification with specialization in Integration, verification tools methodology and SOC signoff.
• Work with a team of Architects, Hardware and Software engineers to Define the product use case scenarios.
• Strong hands-on experience in different SOC Verification activities, UVM System Verilog, kv, X86, C++, HW/SW co-verification, Test plan review, Debug/triage, Coverage, bottleneck resolution, Strong Problem Solving, Automation and Debugging Skills, System bus protocol understanding including some of the common IPs like ACE, CHI, AXI, PCIe, Ethernet, Low speed peripherals, NOC, DDR, memory controller, ARMSS, X86 etc.
• Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc.
• Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence.
• Expertise in managing execution team, project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks identification and mitigation plan.
• JIRA based project management is a plus.

ACADEMIC CREDENTIALS:

• BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE
• ~15-20 years of strong DV experience in IP, Sub System SOC Verification, IP deployment/integration.
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