Senior Design Verification Engineer (ASIC/SoC)

As a Senior Design Verification Engineer, you will be responsible for building UVM-based testbenches from scratch and contributing to multiple successful tapeouts. Your deep expertise in functional verification using SystemVerilog and UVM will be essential, along with owning verification deliverables end-to-end. Key Responsibilities: - Develop UVM-based testbenches from scratch - Contribute to multiple successful tapeouts - Utilize strong hands-on experience with SystemVerilog and UVM methodology - Apply solid knowledge of SoC/ASIC architecture and verification lifecycle - Write testbenches, stimulus, checkers, monitors, and scoreboards - Demonstrate strong debugging skills using simulation tools like VCS, Questa - Implement functional and code coverage techniques - Utilize familiarity with Register Abstraction Layer (RAL) modeling and verification - Apply excellent analytical and problem-solving skills - Demonstrate strong communication and teamwork abilities Qualifications Required: - B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related fields - 4-10 years of relevant experience in ASIC/SoC design verification - Must have contributed to at least three or more successful tapeouts If there are any additional details about the company in the job description, please provide them.,