Senior Design Verification Engineer (ASIC/SoC)

As a Senior Design Verification Engineer, you will be responsible for designing and implementing UVM-based testbenches from scratch and playing a crucial role in the successful tapeouts of multiple projects. Your expertise in functional verification using SystemVerilog and UVM will be essential in owning verification deliverables end-to-end. Your experience should demonstrate a strong command over SystemVerilog and UVM methodology, coupled with a solid understanding of SoC/ASIC architecture and the verification lifecycle. You will be expected to write testbenches, develop stimulus, checkers, monitors, and scoreboards, and utilize simulation tools like VCS and Questa for debugging purposes. In addition, your familiarity with functional and code coverage, as well as Register Abstraction Layer (RAL) modeling and verification, will be vital in ensuring the quality and completeness of the verification process. Your excellent analytical and problem-solving skills will be put to the test as you work collaboratively within a team environment to achieve project goals. To qualify for this role, you must hold a B.E/B.Tech or M.E/M.Tech degree in Electronics, Electrical, or a related field, along with 4 to 10 years of relevant experience in ASIC/SoC design verification. A track record of contributing to at least three or more successful tapeouts will further strengthen your candidacy for this position.,