Senior Design and Verification Engineer

As a Senior Verification Engineer at Suresh Chips and Semiconductor (SCHIPSEMI), located in Muzaffarpur, you will play a crucial role in ensuring the functional verification of complex designs. Your responsibilities will include developing test plans, debugging designs, validating silicon processes, and ensuring compliance with design specifications. Collaboration with cross-functional teams will be essential to ensure flawless execution in pre-silicon design stages. Key Responsibilities: - Execute IP/SS verification of complex blocks like CPU SS - Verify Fabric/NOC/Interconnect blocks - Proficiency in protocols such as AMBA suite (AXI-4, AHB), PCIe (preferably Gen5, Gen6), CXL, DDR, interrupt handling, and power management - Strong command over System Verilog (SV), Universal Verification Methodology (UVM), test bench component development (BFM, Scoreboard, Checkers, Monitors), assertions, test plans, and coverage & assertions - Demonstrated debugging skills - Utilize scripting knowledge in languages like Python, Perl, etc. - Perform SOC DV, CPU DV, and Bus Interconnects verification - Familiarity with ARM v8/v9, RISC-V, x86 Architecture, Memory Architecture (DRAM, Cache, MMU), Cache Coherent Architectures, AXI, PCIe, DDR/HBM - Understand architecture and micro-architecture specifications - Develop scalable Test benches in System Verilog and UVM - Create Tests, Functional Coverage Models, and System Verilog Assertions - Proficient in System Verilog, UVM, OVM, OOP/C++, and Python scripting Qualifications Required: - Experience in IP Verification - Strong background in executing IP/SS verification of complex blocks - Knowledge of Fabric/NOC/Interconnect blocks verification - Proficiency in protocols such as AMBA suite, PCIe, CXL, DDR, interrupt handling, and power management - Excellent skills in System Verilog, UVM, test bench development, assertions, and coverage & assertions - Scripting knowledge in Python, Perl, etc. - Familiarity with SOC verification, CPU DV, Bus Interconnects, ARM, RISC-V, x86 Architecture, Memory Architecture, Cache Coherent Architectures, AXI, PCIe, DDR/HBM - Ability to develop scalable Test benches, Tests, Functional Coverage Models, and System Verilog Assertions - Proficiency in System Verilog, UVM, OVM, OOP/C++, and Python scripting Join SCHIPSEMI in shaping the future of semiconductor technology and be a part of groundbreaking projects in a culture of technical mastery.,