Senior Verification Engineer

As a Senior Verification Engineer at Suresh Chips and Semiconductor (SCHIPSEMI) in Muzaffarpur, your role will involve functional verification of complex designs, including developing test plans, debugging designs, validating silicon processes, and ensuring compliance with design specifications. You will collaborate closely with cross-functional teams to ensure flawless execution in pre-silicon design stages. Key Responsibilities: - Execute IP/SS verification of complex blocks (CPU SS) - Verify Fabric/NOC/Interconnect blocks - Utilize protocols such as AMBA suite (AXI-44/AHB), PCIe (preferably Gen5, Gen6), CXL, DDR, interrupt handling, and power management - Proficient in System Verilog (SV), Universal Verification Methodology (UVM), test bench component development (BFM, Scoreboard, Checkers, Monitors), assertions, test benches, test plans, and coverage & assertions - Demonstrate excellent debugging skills - Apply scripting knowledge in Python, Perl, etc. - Perform SOC DV, CPU DV, Bus Interconnects verification - Work with ARM v8/v9, RISC-V, x86 Architecture - Understand Memory Architecture (DRAM, Cache, MMU) and Cache Coherent Architectures - Validate AXI, PCIe, DDR/HBM interfaces - Develop scalable Test benches (BFM, Scoreboard, Checkers, Monitors) in System Verilog and UVM - Create Tests, Functional Coverage Models, and System Verilog Assertions - Proficiency in System Verilog/UVM/OVM, OOP/C++, and Python scripting - Exhibit excellent debugging skills Qualifications Required: - Experience in IP Verification - Strong background in executing IP/SS verification of complex blocks (CPU SS) - Knowledge of Fabric/NOC/Interconnect blocks verification - Familiarity with protocols such as AMBA suite (AXI-44/AHB), PCIe (preferably Gen5, Gen6), CXL, DDR, interrupt handling, and power management - Expertise in System Verilog (SV), Universal Verification Methodology (UVM), test bench component development (BFM, Scoreboard, Checkers, Monitors), assertions, test benches, test plans, and coverage & assertions - Strong debugging skills - Proficiency in scripting languages like Python, Perl, etc. - Experience in SOC DV, CPU DV, Bus Interconnects verification - Knowledge of ARM v8/v9, RISC-V, x86 Architecture - Understanding of Memory Architecture (DRAM, Cache, MMU) and Cache Coherent Architectures - Proficiency in AXI, PCIe, DDR/HBM interfaces - Ability to develop scalable Test benches (BFM, Scoreboard, Checkers, Monitors) in System Verilog and UVM - Competency in creating Tests, Functional Coverage Models, and System Verilog Assertions - Proficiency in System Verilog/UVM/OVM, OOP/C++, and Python scripting - Strong debugging skills,