Semiconductor Design Engineer

You should have 5 to 8 years of experience in the field. Your responsibilities will include having hands-on experience in developing and understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, and transient analysis. You should be able to decipher circuit behavior from schematics and be familiar with circuit characterization, timing libraries files and formats, and timing arcs. Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations is required. Familiarity with static timing analysis is also necessary. Additionally, you should have hands-on experience in Gate level simulations with SDF back annotation, debugging SDF annotation issues, and ensuring good annotation coverage. It is important to have experience with latch-based designs and their timing requirements, debugging Gate level simulation failures, and root causing the failures to actual circuits. You should be able to accomplish what-if analysis by making changes and ensuring that the fix can solve the issue. Hands-on know-how of System Verilog Assertions to specify expected design behavior is expected, and familiarity with UVM is a plus. Strong communication skills are essential for this role, with the ability to convey complex technical concepts to other design peers in verbal and written form. The responsibilities also include gate level simulation, spice correlation, debugging failures, and providing fixes at gate or transistor level as applicable.,