Semiconductor Design Engineer

As an experienced IC Design Engineer (5-8 years), you will be responsible for the following: - Hands-on experience in developing and understanding building block schematics, memory schematics, and running circuit simulations with spice simulators. You should be proficient in DC analysis and transient analysis. - Ability to decipher circuit behavior from schematics and familiarity with circuit characterization, timing libraries files and formats, as well as timing arcs. - Experience in Verilog MOS switch level models and netlist simulation, including zero delay, unit delay, and path delay simulations. - Familiarity with static timing analysis and gate level simulations with SDF back annotation. - Proficiency in debugging SDF annotation issues and ensuring good annotation coverage. - Hands-on experience with latch-based designs and their timing requirements. - Capable of debugging gate level simulation failures and identifying root causes of failures in actual circuits. - Skilled in conducting what-if analysis by implementing changes to resolve issues effectively. - Knowledge of System Verilog Assertions to specify expected design behavior, with familiarity with UVM considered a plus. - Strong communication skills to effectively convey complex technical concepts to other design peers both verbally and in written form. - Ability to correlate gate level simulation with spice, debug failures, and provide fixes at gate or transistor level as necessary. If you are excited about working in a challenging environment that values innovation and collaboration, this opportunity at hirist.tech could be the next step in your career.,