Principal IO Mixed Signal Design Engineer Microchip Technology

10.0 - 14.0 years

0 Lacs

hyderabad, telangana

On-site

Role Overview: Are you looking for a unique opportunity to be a part of something great at Microchip Technology Inc. As a mixed signal design engineer, you will be responsible for the integration and verification of mixed signal blocks in high-speed IOs in FPGAs. Your role will involve floor planning, place and route, timing closure, and integration of mixed signal blocks in the IOs. Key Responsibilities: - Responsible for the integration of mixed signal blocks in the IO, including generating constraint files, floor planning, place and route of performance critical digital blocks in the IO signal path, and timing closure using STA. - Develop and integrate custom mixed signal circuits for hig...

Posted 1 week ago

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Semi conductor design engineer 1 SysTechCorp Inc

1.0 - 3.0 years

0 Lacs

hyderabad, telangana, india

On-site

Semiconductor Design Engineer 1_INR Details: Experience: 1yrs to 3yrs. Location: Hyderabad JD: Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis. Experience in deciphering circuit behavior from schematics. Familiarity with circuit characterization, timing libraries - files and formats, timing arcs Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations. Familiarity with static timing analysis Hands-on experience in Gate level simulations with SDF back annotation. Debug SDF annotation issues and ensur...

Posted 1 month ago

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Semiconductor Design Engineer Creeno Solutions Pvt Ltd

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

As an experienced IC Design Engineer (5-8 years), you will be responsible for the following: - Hands-on experience in developing and understanding building block schematics, memory schematics, and running circuit simulations with spice simulators. You should be proficient in DC analysis and transient analysis. - Ability to decipher circuit behavior from schematics and familiarity with circuit characterization, timing libraries files and formats, as well as timing arcs. - Experience in Verilog MOS switch level models and netlist simulation, including zero delay, unit delay, and path delay simulations. - Familiarity with static timing analysis and gate level simulations with SDF back annotatio...

Posted 1 month ago

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Semiconductor Design Engineer Creeno Solutions Pvt Ltd

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

You should have 5 to 8 years of experience in the field. Your responsibilities will include having hands-on experience in developing and understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, and transient analysis. You should be able to decipher circuit behavior from schematics and be familiar with circuit characterization, timing libraries files and formats, and timing arcs. Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations is required. Familiarity with static timing analysis is also necessary. Additionally, you should have hands-on experience in Ga...

Posted 3 months ago

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