Semiconductor Design Engineer Creeno Solutions Pvt Ltd

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

You should have 5 to 8 years of experience in the field. Your responsibilities will include having hands-on experience in developing and understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, and transient analysis. You should be able to decipher circuit behavior from schematics and be familiar with circuit characterization, timing libraries files and formats, and timing arcs. Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations is required. Familiarity with static timing analysis is also necessary. Additionally, you should have hands-on experience in Gate level simulations with SDF back annotation, debugging SDF annotation issues, and ensuring good annotation coverage. It is important to have experience with latch-based designs and their timing requirements, debugging Gate level simulation failures, and root causing the failures to actual circuits. You should be able to accomplish what-if analysis by making changes and ensuring that the fix can solve the issue. Hands-on know-how of System Verilog Assertions to specify expected design behavior is expected, and familiarity with UVM is a plus. Strong communication skills are essential for this role, with the ability to convey complex technical concepts to other design peers in verbal and written form. The responsibilities also include gate level simulation, spice correlation, debugging failures, and providing fixes at gate or transistor level as applicable.,

Posted 2 weeks ago

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Semiconductor Design Engineer LeadSoc Technologies Pvt Ltd

5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

As a Design Verification Engineer at our Hyderabad location, you will be responsible for verifying the design of industry-leading products, such as Graphics DDR7. With 5-7 years of experience in SV, UVM, Test Bench Development, Soc, Full-chip verification, and memory experience, you will play a crucial role in ensuring the quality and reliability of our products. Your primary responsibilities will include Verilog simulation, UVM methodology implementation, and full-chip verification. Familiarity with memory interfaces is highly preferred. Additionally, you will have the opportunity to work on projects involving GLS, STA, Python knowledge, and circuit characterization. We are looking for someone with a quick learning ability, a positive attitude, and strong technical skills in system Verilog and UVM. Your educational background should include a bachelor's degree, and any experience in static timing analysis, GLS, and Python automation for test bench development will be advantageous. Strong communication skills are essential for this role, as you will be required to effectively convey complex technical concepts to your peers. A proactive learner with strong analytical and problem-solving skills will thrive in this dynamic environment. If you are a local candidate and an immediate joiner with a passion for design verification and a desire to work on cutting-edge products, we would love to hear from you. Join us in our mission to deliver high-quality products to our customers and make a significant impact in the industry.,

Posted 1 month ago

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