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TekWissen
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RTL Lead Engineer

RTL Lead Engineer

TekWissen

6 - 9 years

0 Lacs

Mysuru

Posted:1 month ago| Platform:

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Skills Required

Perl TCL Python SystemVerilog RTL Coding RTL Design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Overview:

TekWissen is a global workforce management provider throughout India and many other countries in the world.

Position: RTL Lead Engineer

Location: Mysore

Work Type: Onsite

Strong proficiency in Verilog and SystemVerilog, with experience in designing finite state machines (FSMs), clocking, reset strategies, and bus architectures.
Capable of developing microarchitecture from specification to RTL, including block and subsystem design, as well as thorough documentation.
Skilled in RTL debugging, with working knowledge of synthesis processes and timing closure.
Familiar with industry protocols and integration, such as AXI, APB, AHB, PCIe, SoC integration, design-for-test (DFT), and power domain management.

Good to Have Skills:

Experience with scripting and automation using Python, Tcl, or Perl to streamline design flows.
Demonstrated leadership and collaboration abilities, including mentoring, cross-functional communication, AMS integration, UPF-based low-power design, post-silicon debugging, and a proactive approach to automation

TekWissen Group is an equal opportunity employer supporting workforce diversity.

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