Register Transfer Level Engineer (RTL)

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements.
Responsibilities:1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications.2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture.3. Perform design optimizations for area, power, and performance.4. Conduct design reviews and ensure compliance with coding standards and best practices.5. Work closely with verification teams to develop test plans and ensure 100% functional coverage.6. Debug and resolve design and integration issues during simulation and post-silicon validation.7. Participate in timing analysis and closure in collaboration with the physical design team.8. Document design specifications, test cases, and user guides for IP and SoC designs.Requirements:1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field.2. 210 years of experience in RTL design and implementation for VLSI systems.3. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies.4. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques.5. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent.Proficiency in scripting languages (Python, Perl, TCL) for design automation.6. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR.7. Experience in static timing analysis (STA) and timing closure workflows.8. Strong problem-solving skills and the ability to debug complex design issues.9. Excellent communication and collaboration skills to work effectively in a team environment.Preferred Qualifications:1. Experience with low-power design and multi-clock domain systems.2. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies.3. Exposure to formal verification methodologies.Experience in hardware-software co-design and FPGA prototyping.4. Familiarity with machine learning or AI-based RTL optimizations.How to Apply:If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.