Principal Design Engineer

At Cadence, we are seeking individuals who are passionate about technology and aspire to lead and innovate in the field. As a design and verification engineer, you will play a crucial role in making a significant impact on the world of technology. The ideal candidate should hold a BE/BTech/ME/MTech degree in Electrical, Electronics, or VLSI with a minimum of 8 years of experience in Design Verification, specifically with SV/UVM. A strong foundation in functional verification fundamentals, including environment planning, test plan generation, and environment development, is essential for this role. In this position, you will be responsible for verifying complex designs and leading projects from concept to verification closure. Proficiency in UVM and System Verilog coding, as well as experience in functional verification environment development, are key requirements for this role. Additionally, prior experience in IP verification of memory IP such as DDR, HBM, or GDDR would be considered a valuable asset. Join us at Cadence, where we are committed to tackling challenges that others may find insurmountable. Your contributions will be instrumental in solving problems that truly matter in the realm of technology.,