Physical Design Engineer

Greeting with HCL Tech! We were looking somebody who is having experience in Physical design Experience: 4 to 10 Years Location: Kochi JD#1 : 4-6years Tapeout experience in block level PnR implementation including synthesis for medium to complex blocks Good to have experience in TSMC/Intel lower technology node(16/14nm or below) Experience in independently analyzing/resolving congestion, timing issues and basic understanding of clock tree build Basic Timing understanding to independently analyze timing paths Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage Basic equivalency check understanding. Good to have Conformal LEC experience. Should have understanding of basic shell scripting, tool based TCL scripting to automate redundant tasks JD#2 : 6-10years Tapeout experience in full chip floorplan/full chip partitioning flow. Experience in die-size estimation spread sheet IP based and synthesis based Experience in IO/Bump planning & placement, custom analog/PG planning and route implementation Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage Experience in RDL routing Experience in interfacing with cross functional teams and block PnR teams Good understanding of basic shell scripting, tool based TCL scripting to automate all custom activities Experience in version control systems Experience in managing/mentoring small teams